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LSI Design for Multi-Valued Static RAM and its Applications

Research Project

Project/Area Number 10650339
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionUniversity of Miyazaki

Principal Investigator

ISHIZUKA Okihiko  Miyazaki University, Faculty of Engineering, Professor, 工学部, 教授 (90040980)

Co-Investigator(Kenkyū-buntansha) TANG Zhen  Toyama University, Faculty of Engineering, Professor (Until 1999), 工学部, 教授 (90227299)
TANNO Koichi  Miyazaki University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (50260740)
Project Period (FY) 1998 – 2000
Project Status Completed (Fiscal Year 2000)
Budget Amount *help
¥2,600,000 (Direct Cost: ¥2,600,000)
Fiscal Year 2000: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1999: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 1998: ¥800,000 (Direct Cost: ¥800,000)
KeywordsFloating Gate / Neuron MOS / Multi-Valued SRAM / LSI Design / Quantizer / Down Literal Circuit / フローティング・ゲート
Research Abstract

In this research, we have developed a high-performed multi-valued static RAM (SRAM) composed of a qauntizer with floating-gate MOS transistors (vMOS). In 1998, we designed down literal circuits using two vMOS's as the fundamental circuits. The quaternary qauntizer was implemented with the down literal circuit and two binary CMOS AND/OR gates. The quaternary SRAM was realized with this qauntizer added control circuits of writing, memorizing and reset. In 1999, we engrossed the layout design of the quaternary qauntizer and required the fabrication of the LSI chip to VDEC.The smallest size of the cell can be realized. The simulation results with HSpice showed the confirmation of the normal operation and the lower speed. Then, we tried to design some vMOS's with various size of input capacitors. In 2000, we examined the fabricated chips. The results of the experiment presented the confirmation of the theoretical operation and the lower speed as same as the simulation results. The problem of the low speed is occurred by the existance of initial charges in the floating gates in a vMOS.Therefore, we can not complete the LSI chip of the multi-valued SRAM.We will try to continue this work, and design the layout of the multi-valued SRAM.On the other hand, down literal circuits using vMOS's has been developed. The performances grows highly, and they are applied to many circuits, such as multi-input variable-threshold circuits, pass gates, multi-level generators, multi-valued MIN circuits and multi-valued complemented circuits. These circuits can used as improvement of a qauntizer and they are necessary to compose a multi-valued SRAM.

Report

(4 results)
  • 2000 Annual Research Report   Final Research Report Summary
  • 1999 Annual Research Report
  • 1998 Annual Research Report
  • Research Products

    (42 results)

All Other

All Publications (42 results)

  • [Publications] J.Shen: "Application of neuron-MOS to current-mode multi-valued logic circuits"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. 28. 128-133 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 安村正之: "多値SRAMの構成と解析"宮崎大学工学部紀要. 第27号. 127-131 (1998)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen: "Neuron-MOS current mirror circuit and its application to multi-valued logic"IEICE Trans.on Information and Systems. E82-D,5. 940-948 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen: "Down literal circuit with neuron-MOS transistors and its applications"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. 29. 180-185 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 首藤真: "量子化回路による4値SRAMの構成と解析"宮崎大学工学部紀要. 第28号. 151-156 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Syuto: "Multiple-valued basic operational circuits with neuron-MOS transistors"Proc.of Int.Symp.on Nonlinear Theory and its Application. 1. 85-88 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] K.Tanno: "Design of multiple-valued logic circuits using neuron-MOS transistors"Proc.of The 9th International Workshop on Post-Binary Ultra-Large-Scale Integration Systems. 28-31 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen: "Multi-valued logic pass gate network using neuron-MOS transistors"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. 30. 15-20 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Syuto: "Multi-input variable-threshold circuits for multi-valued logic functions"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. 30. 27-32 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Inaba: "Characteristics of neuron MOS LSI for multi-valued logic"Proc.of Int.Symp.on Nonlinear Theory and its Application. 1,6-B. 405-408 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Syuto: "Synthesis and Implementation of Multi-Input Variable-Threshold Functions"MULTIPLE-VALUED LOGIC-An International Journal. (採録決定). (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Inaba: "Voltage-Mode Variable Threshold Circuits with Neuron MOS Transistors for Multi-Valued Logic"MULTIPLE-VALUED LOGIC-An International Journal. (採録決定). (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen, K.Tanno, O.Ishizuka, Z.Tang: "Application of neuron-MOS to current-mode multi-valued logic circuits"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. vol.28. 128-133 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.YASUMURA, K.TANNO, Z.TANG, O.ISHIZUKA: "Syntheses and Analyses on Multi-Valued Static Random Access Memory"Memoirs of the Faculty of Engineering, Miyazaki University. No.27. 127-131 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen, K.Tanno, O.Ishizuka, Z.Tang: "Neuron-MOS current mirror circuit and its application to multi-valued logic"IEICE Trans.on Information and Systems. vol.E82-D, no.5. 940-948 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen, K.Tanno, O.Ishizuka: "Down literal circuit with neuron-MOS transistors and its applications"Proc.of.IEEE Int.Symp.on Multiple-Valued Logic. vol.29. 180-185 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.SYUTO, H.MAGATA, K.TANNO and O.ISHIZUKA: "Synthesis and Analysis of a Quaternary Static RAM using Quantizing Circuits"Memoirs of the Faculty of Engineering, Miyazaki University. No.28. 151-156 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Syuto, K.Tanno, O.Ishizuka, Z.Tang: "Multiple-valued basic operational circuits with neuron-MOS transistors"Proc.of Int.Symp.on Nonlinear Theory and its Application. vol.1. 85-88 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] K.Tanno, O.Ishizuka: "Design of multiple-valued logic circuits using neuron-MOS transistors"Proc.of The 9th International Workshop on Post-Binary Ultra-Large-Scale Integration Systems. (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen, K.Tanno, O.Ishizuka: "Multi-valued logic pass gate network using neuron-MOS transistors"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. Vol.30. 15-20 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Syuto, J.Shen, K.Tanno, O.Ishizuka: "Multi-input variable-threshold circuits for multi-valued logic functions"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. Vol.30. 27-32 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] M.Inaba, J.Shen, K.Tanno, O.Ishizuka: "Characteristics of neuron MOS LSI for multi-valued logic"Proc.of Int.Symp.on Nonlinear Theory and its Application. Vol.1, No.6-B. 405-408 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Makoto Syuto, Koichi Tanno and Okihiko Ishizuka: "Synthesis and Implementation of Multi-Input Variable-Threshold Functions"MULTIPLE-VALUED LOGIC-An International Journal. (to be published).. (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Motoi Inaba, Jing Shen, Koichi Tanno and Okihiko Ishizuka: "Voltage-Mode Variable Threshold Circuits with Neuron MOS Transistors for Multi-Valued Logic"MULTIPLE-VALUED LOGIC-An International Journal. (to be published).. (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Shen: "Application of neuron-MOS to current-mode multi-valued logic circuits"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. 28. 128-133 (1998)

    • Related Report
      2000 Annual Research Report
  • [Publications] 安村正之: "多値SRAMの構成と解析"宮崎大学工学部紀要. 第27号. 127-131 (1998)

    • Related Report
      2000 Annual Research Report
  • [Publications] J.Shen: "Neuron-MOS current mirror circuit and its application to multi-valued logic"IEICE Trans.on Information and Systems. E82-D,5. 940-948 (1999)

    • Related Report
      2000 Annual Research Report
  • [Publications] J.Shen: "Down literal circuit with neuron-MOS transistors and its applications"Proc.of IEEE Int.Symp.on Multiple-Valued Iogic. 29. 180-185 (1999)

    • Related Report
      2000 Annual Research Report
  • [Publications] 首藤真: "量子化回路による4値SRAMの構成と解析"宮崎大学工学部紀要. 第28号. 151-156 (1999)

    • Related Report
      2000 Annual Research Report
  • [Publications] M.Syuto: "Multiple-valued basic operational circuits with neuron-MOS transistors"Proc.of Int.Symp.on Nonlinear Theory and its Application. 1. 85-88 (1999)

    • Related Report
      2000 Annual Research Report
  • [Publications] K.Tanno: "Design of multiple-valued logic circuits using neuron-MOS transistors"Proc.of The 9th International Workshop on Post-Binary Ultra-Large-Scale Integration Systems. 28-31 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] J.Shen: "Multi-valued logic pass gate network using neuron-MOS transistors"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. 30. 15-20 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] M.Syuto: "Multi-input variable-threshold circuits for multi-valued logic functions"Proc.of IEEE Int.Symp.on Multiple-Valued Logic. 30. 27-32 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] M.Inaba: "Characteristics of neuron MOS LSI for multi-valued logic"Proc.of Int.Symp.on Nonlinear theory and its Application. 1,6-B. 405-408 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] M.Syuto: "Synthesis and Implementation of Multi-Input Variable-Threshold Functions"MULTIPLE-VALUED LOGIC - An Intertional Journal. (採録決定). (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] M.Inaba: "Voltage-Mode Variable Threshold Circuits with Neuron MOS Transistors for Multi-Valued Logic"MULTIPLE-VALUED LOGIC - An International Journal. (採録決定). (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] J.Shen,K.Yanno,O.Ishizuka: "Down Literal Cirowits with Neuron-MOS transistor and Its Applications"Proc.Int.Symp.on Multiple-Valned Logic. 29. 180-185 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 首藤真,真方弘志,淡野公一,石塚興彦: "量子化回路による4値SRAMの構成と解析"宮崎大学工学部紀要. 28. 151-156 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] M.Syuto,K.Tanno O.Ishizuka,Z.Taug: "Multiple-Valuod basic operational circuits with neuron-MOS transistors"Proc.Int.Symp.on Nonlinear Theory and its Application. 1. 85-88 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] M.Syuto,J.Shen,K.Tomo,O.Ishizuka: "Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Furctions"Proc.Int.Symp.on Multiple-ValuedLogic. 30<採録決定>. (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] Ting Shen, Okihiko Ishizuka et al.: "Down Literal Circuits with Neuron-MOS Transistors and Its Applications" Proc.of Int.Symp.on Multiple-Valuecl Logic. 29<採録決定>. (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] 首藤真、石塚興彦他: "量子化回路による4値SRAMの構成と解析" 宮崎大学工学部紀要. 28<採録決定>. (1999)

    • Related Report
      1998 Annual Research Report

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Published: 1998-04-01   Modified: 2016-04-21  

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