| Budget Amount *help |
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1999: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1998: ¥2,400,000 (Direct Cost: ¥2,400,000)
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| Research Abstract |
In the field of the digital computer arithmetic, various VLSI technologies for realtime processing of large massive binary data at a very high speed have increasingly come into much efficient meaning out of necessity. We have realized new parallel-processing arithmetic and logical operation circuits using redundantly-represented high-radix positive digit numbers, which can be effective to eliminate the chain transferred delay in the carry process of operation with binary numbers having very large digit-lengths because of its fast processing. By utilizing these basic computation technique for avoiding errors arising from the analog calculation in the conventional analog neural an fuzzy hardware systems, we tried to realize high-speed and high-precision digital signal processing circuits.
In 1998, we proposed a new high-speed addition and subtraction algorithm for minimum redundantly-represented high-radix positive digit (PD) numbers which are easy to be transformed into non-redundant bin
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ary numbers, and we realized a new current-mode CMOS-based 5-valued 4-radix PD number addition and subtraction circuit. Furthermore, we realized the fuzzy basic logical operation circuits for logical products, logical sum, bounded sum, bounded difference and bounded product, and max/min discrimination between two redundantly-represented 5-valued 4-radix positive digit numbers which express the fuzzy grades of membership functions.
In 1999, in the fourth chapter, in order to construct the complex system with other binary processing systems, we proposed new binary-coded redundant PD number addition, subtraction method and multiplication methods where each digit value can be expressed a set of plural non-redundant bit values. I construct a new voltage-mode CMOS-based adder and subtracter based on logical combinational switch circuit, which is composed of NOT circuits and NAND circuits. Moreover, I realized a new decoder for converting redundant 4-radix PD numbers into pure binary number by using transforming algorithm which is worked as a carry look ahead addition processing.
We tested the new adder by using general circuit simulation software, SPICE. We have used the SPICE model parameters of the enhancement type PMOS and NMOS based on the 0.5 μm MOSIS CMOS technology. By the measured results, the maximum propagation delay time of addition are obtained about 3 [ns]. Less
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