| Project/Area Number |
10650378
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
情報通信工学
|
|---|
| Research Institution | Shibaura Institute of Technology |
|---|
Principal Investigator |
WATANABE Eiji Shibaura Institute of Technology, Faculty of Systems Engineering, Professor, システム工学部, 教授 (40191746)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
柳澤 健 芝浦工業大学, システム工学部, 教授 (20016314)
|
|---|
| Project Period (FY) |
1998 – 2001
|
| Project Status |
Completed (Fiscal Year 2001)
|
| Budget Amount *help |
¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 2001: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2000: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1999: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 1998: ¥1,300,000 (Direct Cost: ¥1,300,000)
|
|---|
| Keywords | Digital Signal Processor / Complex Signal Processing / Digital Signal Processing / Tranfer Function / Circuit Synthesis / Digital Filter / Prallel Processing / Discrete-Time System |
|---|
| Research Abstract |
The aim of this study is the realization of advanced parallel digital signal processing systems by using complex and hyper-complex coefficient circuits. This study has studied this theme for four years, and obtained following results. A realization of real-coefficient circuits on a complex digital signal processor is proposed. This is a new application of such a processor. The evaluation of its performance is also given. The proposed method is effective to realize such structures that included adders have more than two input branches. An implementation method of the above method on already proposed complex digital signal processor PSI is studied. A new processing mode named "advance mode" is introduced as an improvement of PSI in order to reduce the overhead of real processing. This study also proposes a new structure of complex multipliers with extended input buses. To evaluate the performance of the advance mode, a hardware simulator is developed. It is well known that complex processing units with redundant arithmetics can realize highspeed complex circuits because they have no carry propagation. However, this study shows that the conventional complex units cannot implement real circuits in the advance mode effectively. This study proposes a new complex redundant binary arithmetic suitable for the advance mode. Two types of partial product selectors based this arithmetic are derived.
|
