| Project/Area Number |
10650437
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Control engineering
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| Research Institution | Hachinohe Institute of Technology |
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Principal Investigator |
TOMABECHI Nobuhiro Hachinohe Institute of Technology Faculty of Engineering, Professor, 工学部, 教授 (70048180)
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| Project Period (FY) |
1998 – 1999
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| Project Status |
Completed (Fiscal Year 1999)
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| Budget Amount *help |
¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1999: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1998: ¥1,100,000 (Direct Cost: ¥1,100,000)
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| Keywords | hierarchical redundancy design / WSI / neuro-procossor / yield enhancement / robot / control / 超高集積 / 歩留り改善 / 多次元サブシステム分割法 |
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| Research Abstract |
(1) Design of the Non-Redundant Neuro-Processor
The full-hardware neuro-processor applicable to real time control of intelligent robots is targeted. The architecture design, the logic design, and the layout design of the neuro-processor have been carried out. The operation speed, the chip size, and the number of neurons integrated on a single wafer are estimated.
(2) Presentation of the Hierarchical Redundancy Design
The hierarchical redundancy design methodology suitable for the neuro-processor is presented. This method combines the circuit level redundancy inside a neuron with the system level redundancy using a neuron as the basic building block. Using the method, the yield enhancement of the neuro-processor can be realized with small overhead.
(3) Optimal Design of the Redundant Neuro-Processor
The yield analysis of the neuro-processor applying the hierarchical redundancy design has been carried out and the relationship between system parameters and the yield is made clear. Based on the analysis, the optimal design of the neuro-processor has been done. It is concluded that a 3-layered feed-forward neuro-processor composed of 500 neurons may be implemented on a single wafer with the overhead of 27% and with the yield of 50%.
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