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Decomposition of Large-Scale Logic Functions

Research Project

Project/Area Number 10680360
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKyushu Institute of Technology

Principal Investigator

SASAO Tsutomu  Kyushu Institute of Technology, Department of Computer Science and Technology, Professor, 情報工学部, 教授 (20112013)

Co-Investigator(Kenkyū-buntansha) IGUCHI Yukihiro  Meiji University, Department of Computer Science, Associate Professor, 理工学部, 助教授 (60201307)
KAJIHARA Seiji  Kyushu Institute of Technology, Department of Computer Science and Electronics, Associate Professor, 情報工学部, 助教授 (80252592)
Project Period (FY) 1998 – 2000
Project Status Completed (Fiscal Year 2000)
Budget Amount *help
¥2,600,000 (Direct Cost: ¥2,600,000)
Fiscal Year 2000: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 1999: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 1998: ¥1,400,000 (Direct Cost: ¥1,400,000)
KeywordsFunctional Decomposition / FPGA design / Multilevel Logic Synthesis / Logic Minimization / Multiple-output logic function / Symmetric functions / Time domain multiplexing (TDM) / Multiple-Valued Logic
Research Abstract

9.1 Decomposition System : DECOMP
This part considers a decomposition system for logic functions using three methods : 1) Disjoint bi-decomposition ; 2) Simple disjoint decomposition with a few bound set variables ; and 3) Decomposition using Jacobian. 1) and 2) are quick, but find only limited classes of decompositions, while 3) finds all simple disjoint decompositions by spending more time. We show the experimental results for more than 3000 functions. We also define a new class of functions : complete bi-decomposable functions. Experimental results show that many practical logic functions have disjoint decompositions and some are completely bi-decomposable.
9.2 Decomposition System using an Automatic Test Pattern Generator and a Logic Simulator
Since this method uses netlists rather than binary decision diagrams to represent logic functions, it can decompose larger networks. By using information of netlists, it efficiently finds decompositions of form f (X_1, X_2)=g (h (X_1), X_2), whe … More re |X_1|【less than or equal】k. The computation time is proportional to Gn^k, where n is the number of primary input variables, and G be the number of gates.
9.3 Arithmetic Ternary Decision Diagrams
In the arithmetic ternary decision diagram (arith_TDD), the third edge denotes f_2=f_0+f_1, where + is an integer addition. The arith_TDD represents the extended weight function, an integer function showing the numbers of true minterms in the cubes. The arith_TDD is useful to detect functional decompositions, prime implicants and prime implicates. Experimental results compare the size of BDDs and various TDDs for benchmark functions.
9.4 Three Parameters Find Functional Decompositions
This part shows a heuristic method to find the partitions of input variables. We introduce three parameters to find bipartitions of input variables.
9.5 Method to Find Undecomposable Functions
A function f(X) has a decomposition if f is represented as f (X_1, X_2)=g (h (X_1), X_2). This part shows an method to detect partitions (X_1, X_2) that do not produce decompositions for f(X). It quickly reduces the search space for the decompositions by using look-up tables for undecomposable functions. A systematic method to find decompositions is presented. This method proves undecomposability of randomly generated functions in linear time.
9.6 An Expansion of Symmetric Functions and Its Application to Non-Disjoint Functional Decompositions
This part presents a new expansion method symmetric functions. It also shows the realizations of rd73, rd84, and 9sym, that require only 4, 6, and 6 LUTs, respectively.
9.7 FPGA Design using Pseudo-Kronecker Decision Diagrams
This method uses both functional decomposition and a mapping to LUT network by using PKDDs. The algorithm consists of the following steps : 1) Decompose the BDD for the given function f into several smaller BDDs ; 2) Transform each BDD into a PKDD ; 3) Partition the PKDD ; and 4) Convert the PKDD into a LUT network ; 5)Simplify the resulting LUT network. This method has the following features : 6) It treats multiple-output function ; 7) The number of the nodes in the PKDD is the upper bound on the number of LUTs ; and 8) For the function without functional decompositions, this method produces much smaller networks than previously reported ones. A prototype of the system has been developed. Experimental results using benchmark functions show the encouraging results.
9.8 Functional Decomposition and Two-level Logic Minimization
A function f is AND bi-decomposable if it can be written as f (X_1, X_2)=h_1 (X_1) h_2 (X_2). In this case, a sum-of-products expression (SOP) for f is obtained from minimum SOPs (MSOP) for h_1 and h_2 by applying distributive laws. If the result is an MSOP, then the complexity of minimization is reduced. However, the application of distributive laws to MSOPs for h_1 and h_2 does not always produce an MSOP for f. In this part, we show an incompletely specified function of n (n-1) variables with an MSOP of only n products, that produces 2^<n-1> Products in the SOP that is obtained by applying distributive laws to the MSOPs of the component functions.
Then, we introduce a new class of logic functions, called orthodox functions, where the application of distributive laws to MSOPs for component functions of f does produce an MSOP.In an orthodox function, the number of products in an MSOP is equal to the size of the maximal independent set of minterms. We show that orthodox functions include all functions with three or fewer variables, all symmetric functions, all unate functions, many benchmark functions, and few random functions with many variables.
9.9 Cascade Realization of Multiple-output Functions by Reconfigurable Hardware
A realization of multiple-output logic function using a large look-up table (LUT) and a sequencer is presented. First, a multiple-out function is represented by an encoded characteristic function for non-zero outputs (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). And finally, the cascade is simulated by a large LUT and a sequencer. We represent multiple-output functions for benchmark functions by cascades of LUTs, and show the number of LUTs and levels of networks. Less

Report

(4 results)
  • 2000 Annual Research Report   Final Research Report Summary
  • 1999 Annual Research Report
  • 1998 Annual Research Report
  • Research Products

    (52 results)

All Other

All Publications (52 results)

  • [Publications] Hafiz Md.Hasan Babu: "Heuristics to minimize multiple-valued decision diagrams"IEICE Trans.Fundamentals. E83-A・12. 2498-2504 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hideyuki Ichihara: "On Processing Order for Obtaining Implication Relations in Static Learning"IEICE Trans.Info.and Syst.. E83-D・10. 1908-1911 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 浅川毅: "トランジション故障を検出するBIST指向テストパターン発生回路"電子情報通信学会論文誌D-I. J84-D-I・2. 165-172 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 井口幸洋: "決定グラフに基づく論理関数の評価システム"電子情報通信学会論文誌D-I. (採録決定). (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 梶原誠司: "最小テスト集合でテスト可能な加算器について"情報処理学会論文誌. (採録決定). (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Y.Iguchi, T.Sasao, and M.Matsuura: "On properties of Kleene TDDs."IEICE Trans.Information and Systems. Vol.E81-D, No.7. 716-723 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Shared multi-terminal binary decision diagrams for multiple-output functions"IEICE Trans.Fundamentals. Vol.E81-A, No.12. 2545-2553 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Time-division multiplexing realizations of multiple-output functions based on shared multi-terminal multiple-valued decision diagrams"IEICE Trans.Information and Systems. Vol.E81-D, No.5. 925-932 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Representations of multiple-output functions using binary decision diagrams for characteristic functions"IEICE Trans.Fundamentals. Vol.E82-A, No.11. 2398-2406 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Heuristics to minimize multiple-valued decision diagrams"IEICE Trans.Fundamentals. Vol.E83-A, No.12. 2498-2504 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hideyuki Ichihara, Seiji Kajihara, and Kozo Kinoshita: "On Processing Order for Obtaining Implication Relations in Static Learning"IEICE Trans.Info.and Syst.. Vol.E83-D, No.10. 1908-1911 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Design of multiple-output networks using time domain multiplexing and shared multi-terminal multiple valued decision diagrams"IEEE International Symposium on Multiple-Valued Logic, Fukuoka, Japan, May 27-29. 45-51 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] J.Butler and T.Sasao: "On the properties of multiple-valued functions that are symmetric in both variable values and labels"IEEE International Symposium on Multiple-Valued Logic, Fukuoka, Japan, May 27-29. 83-88 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Representations of multiple-output logic functions by binary decision diagrams for characteristic functions"the Eighth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'98), Sendai, Japan, Oct.19-20. 101-108 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Sasao and M.Matsuura: "DECOMPOS : An integrated system for functional decomposition"ACM/IEEE International Workshop on Logic Synthesis, Lake Tahoe, CA. (1998)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Y.Iguchi, T.Sasao, M.Matsuura, and A.Iseno: "Realization of regular ternary logic functions using double-rail logic"Asia and South Pacific Design Automation Conference, ASP-DAC'99. 331-334 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "Fast Boolean matching under variable permutation using representative"Asia and South Pacific Design Automation Conference, ASP-DAC'99. 359-362 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Sasao: "Totally undecomposable functions : applications to efficient multiple-valued decompositions"IEEE International Symposium on Multiple-Valued Logic, Freiburg, Germany, May 20-23. 59-65 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Shared multiple-valued decision diagrams for multiple-output functions"IEEE International Symposium on Multiple-Valued Logic, Freiburg, Germany, May 20-23. 166-172 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] D.Debnath ana T.Sasao: "Multiple-valued minimization to optimize PLA with output parity gates"IEEE International Symposium on Multiple-Valued Logic, Freiburg, Germany, May 20-23. 99-104 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Sasao and S.Kajihara: "Functional decompositions using an automatic test pattern generator and a logic simulator"ACM/IEEE International Workshop on Logic Synthesis, Lake Tahoe, CA. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Sasao: "Arithmetic ternary decision diagrams and their applications"Fourth International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, (Reed-Muller 99), Victoria, Canada, August 20-21. 149-155 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "Exact minimization of FPRMs for incompletely specified logic functions"Fourth International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, (Reed-Muller 99), Victoria, Cacada, August 20-21. 253-264 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Sasao and K.Kurimoto: "Three parameters to find functional decompositions"Asia and South Pacific Design Automation Conference (ASP-DAC'2000), Jan.26-28, Yokohama, Japan. 259-264

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] D.Debnath and T.Sasao: "Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions"Asia and South Pacific Design Automation Conference (ASP-DAC'2000), Jan.26-28, Yokohama, Japan. 247-252

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Y.Igushi, T.Sasao, M.Matsuura, and A.Iseno: "A hardware simulation engine based on decision diagrams"Asia and South Pacific Design Automation Conference (ASP-DAC'2000), Jan.26-28, Yokohama, Japan. 73-76

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hassan Babu and T.Sasao: "Minimization of multiple-valued decision diagrams using sampling method"Proceedings of the Synthesis and System Integration of Mixed Technologies (SASIMI 2000), April 6-7, Kyoto, Japan.

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hassan Babu and T.Sasao: "Representations of multiple-output switching functions using multiple-valued pseudo-Kronecker decision diagrams"30th International Symposium on Multiple-Valued Logic, Portland, Oregon, U.S.A., May 23-25. (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Sasao: "On the number of dependent variables for incompletely specified multiple-valued functions"30th International Symposium on Multiple-Valued Logic, Portland, Oregon, U.S.A., May 23-25. (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Y.Iguchi, T.Sasao and M.Matsuura: "Implementation of multiple-output functions using PROMDDs"30th International Symposium on Multiple-Valued Logic, Portland, Oregon, U.S.A., May 23-25. (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] T.Sasao: "A New expansion of symmetric functions and their application to non-disjoint functional decompositions for LUT-type FPGAs"Internatioanl Workshop on Logic Synthesis, Dana Point, California, U.S.A., May 31-June 2. (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] I.Sasao and J.T.Butler: "On the minimization of SOPs for bi-decomposable functions"Asia and South Pacific Design Automation Conference (ASP-DAC'2001), Jan.30-Feb.2, Yokohama, Japan. 219-224 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] "Switching Theory for Logic Synthesis"Kluwer Academic Publisher. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hafiz Md.Hasan Babu: "Heuristics to minimize multiple-valued decision diagrams"IEICE Trans.Fundamentals. E83-A・12. 2498-2504 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] Hideyuki Ichihara: "On Processing Order for Obtaining Implication Relations in Static Learning"IEICE Trans.Info.and Syst.. E83-D・10. 1908-1911 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 浅川毅: "トランジション故障を検出するBIST指向テストパターン発生回路"電子情報通信学会論文誌D-I. J84-D-I-2. 165-172 (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 井口幸洋: "決定グラフに基づく論理関数の評価システム"電子情報通信学会論文誌D-I. (採録決定). (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 梶原誠司: "最小テスト集合でテスト可能な加算器について"情報処理学会論文誌. (採録決定). (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 市原英行: "テスト数制限下でのテスト生成手法について"電子情報通信学会論文誌D-1. J98-D-1・7. 861-868 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 梶原誠司: "論理回路における遅延テスト不要パスの高速導出法"電子情報通信学会論文誌D-1. J98-D-1・7. 888-896 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Hafiz Md.Hasan Babu: "Representations of multiple-output functions using binary decision deagrams for characteristic functions"IEICE Trans.Fundamentals. E82-A・11. 2398-2406 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Hafiz Md.Hasan Babu: "Time-division multiplexing realizations of multiple-output functions based on shared multi-terminal multiple-valued decision deagrams"IEICE Trans.Inrormation and Systems. E82-D・5. 925-932 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 井口幸洋: "入力の一部が不明である場合の論理関数のハードウェアを用いた評価法"電子情報通信学会論文誌. J82-D-1・7. 834-842 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] T.Sasao: "Switching Theory for Logic Synthesis"Kluwer academic Publishers. 362 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Time-division multiplexing real izations of multiple-output functions based on shared multi-terminal multiple-valued decisoin diagrams" IEICE Trans.Information and Systems. Vol.E82-D No.5(accepted). (1999)

    • Related Report
      1998 Annual Research Report
  • [Publications] Y.Iguchi,T.Sasao,M.Matsuura,A.Iseno: "Realization of regular ternary logic functions using double-rail logic" Asia and South Pacific Design Automation Conference ASP-DAC'99. 331-334 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] D.Debnath and T.Sasao: "Fast Boolean matching under variable permutation using representative" Asia and South Pacific Design Automation Conference,ASP-DAC'99. 359-362 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao: "Shared multi-terminal binary decision diagrams for multiple-output functions" IEICE Trans.Fundamentals. Vol.E81-A No.12. 2545-2553 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] Y.Iguchi,T.Sasao,and M.Matsuura: "On properties of Kleene TDDs" IEICE Trans.Information and Systems. Vol.E81-D No.7. 716-723 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] Hafiz Md.Hasan Babu and T.Sasao,: "Design of multiple-output networks using time domain multiplexing and shared multi-terminal multiple valued decision diagrams" IEEE International Symposium on Multiple-Valued Logic Fukuoka. 45-51 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] 笹尾勤: "論理設計:スイッチング回路理論(第2版)" 近代科学社, 290 (1998)

    • Related Report
      1998 Annual Research Report
  • [Publications] T.Sasao: "Switching Theory for Logic Synthesis" Kluwer Academic Publisher, 362 (1999)

    • Related Report
      1998 Annual Research Report

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Published: 1998-04-01   Modified: 2016-04-21  

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