| Project/Area Number |
11305026
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Tohoku University |
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Principal Investigator |
TSUBOUCHI Kazuo Tohoku Univ., RIEC, Professor, 電気通信研究所, 教授 (30006283)
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| Co-Investigator(Kenkyū-buntansha) |
NAKASE Hiroyuki Tohoku Univ., RIEC, Research Associate, 電気通信研究所, 助手 (60312675)
横山 道央 東北大学, 電気通信研究所, 助手 (40261573)
益 一哉 東北大学, 電気通信研究所, 助教授 (20157192)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥40,140,000 (Direct Cost: ¥38,700,000、Indirect Cost: ¥1,440,000)
Fiscal Year 2001: ¥6,240,000 (Direct Cost: ¥4,800,000、Indirect Cost: ¥1,440,000)
Fiscal Year 2000: ¥14,500,000 (Direct Cost: ¥14,500,000)
Fiscal Year 1999: ¥19,400,000 (Direct Cost: ¥19,400,000)
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| Keywords | 3D System on a chip / RF / Analog / Digital / All digital modem / Vertical bus line / Flip chip bonding / Au-Au contact / 電流モード回路LSI / オールディジタルモデム / マイクロバンプ実装 / SS-CDMAネットワーク / グローバルインテグレーション / デジタルアナログ混載 / システムトップダウン設計 / ハイブリッド集積化実装 / マイクロバンプ / ワイヤレスマルチメディア / アナログ混在 / チップサイズパッケージング |
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| Research Abstract |
In this research, we have investigated Si CMOS based mixed signal system LSI toward RF-CMOS system on a chip (SOC) for mobile terminal of next generation. Basic components such as FFT circuit with low power operation, SAW device, RF CMOS circuit, and low power digital LSI are studied. Especially, significant results about Si RF CMOS power amplifier, all digital 1-chip modem and packaging technology for 3D system chip have been obtained. We have proposed and confirmed the Si RF CMOS power amplifier operation using B-class push-pull construction with optimum design of n/p-MOSSFET. The power efficiency is more than 50 % and ACPR is less than -33dBc, which have been matched with W-CDMA. All digital 1-chip modem has been implemented with the area of 150x150 um^2. The divided digital clock has been used for RF carrier. The transmission performance with 1 dB degradation from theoretical value has been measured using Si LSI, which has been fabricated using 0.25 um Si process. We proposed the new concept of 3D package and vertical bus line with delay time limitation control method. Contact strength using flip-chip bonding as a basic flip-chip mounting technology has been evaluated. We have experimentally confirmed that Au-Au contact is the best solution for flip-chip bonding.
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