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Study on Design Methodologies for Scalable System-LSI Architectures

Research Project

Project/Area Number 11308011
Research Category

Grant-in-Aid for Scientific Research (A).

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKyushu University

Principal Investigator

MURAKAMI Kazuaki  Kyushu University, Grad.School of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (10200263)

Co-Investigator(Kenkyū-buntansha) SAWADA Sunao  Kyushu University, Grad.School of ISEE, Research Associate, 大学院・システム情報科学研究院, 助手 (70235464)
IWAIHARA Mizuho  Kyushu University, Grad.School of ISEE, Associate Professor, 大学院・システム情報科学研究院, 助教授 (40253538)
YASUURA Hiroto  Kyushu University, Grad.School of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
ISHIHARA Tohru  Univ.of Tokyo, VDEC, Research Associate, 大規模集積システム設計教育研究センター, 助手 (30323471)
廣瀬 啓  九州大学, 大学院・システム情報科学研究科, 日本学術振興会特別研究員
Project Period (FY) 1999 – 2000
Project Status Completed (Fiscal Year 2000)
Budget Amount *help
¥30,700,000 (Direct Cost: ¥30,700,000)
Fiscal Year 2000: ¥5,000,000 (Direct Cost: ¥5,000,000)
Fiscal Year 1999: ¥25,700,000 (Direct Cost: ¥25,700,000)
Keywordssystem LSI / emulation / design optimization / FPGA / low power design / computer architecture / HW / SW codesign / dynamic optimization / 分散演算
Research Abstract

The objective of this research project is to develop design methodologies for scalable system-LSI architectures. The project has performed the following research results.
(1) Development of scalable system-LSI emulator : The project has developed an emulator, which consists of a CPCI-based PC card and two FPGA-mounted CPCI cards, for enabling designers to explore large design space of system-LSI quickly.
(2) Development of architectures for scalable system-LSI and the design space : The project has developed a couple of technologies good for scalable system-LSI, such as (i) PPRAM (Parallel Processing RAM) architectures (inter-LSI communication interface, dynamically variable line-size cache, and so on), (ii) optimizing techniques for variable datapath/memorypath width, (iii) techniques for alleviating data/control dependences on CMP (chip multiprocessor), (iv) intra-LSI signaling technique reducing the effect of crosstalk.
(3) Development of CAD tools : The project has developed a couple … More of CAD tools, such as (i) realtime online profiler for detecting program hot-spots, (ii) hardware/software codesign environment for soft-core processor and Valen-C programs.
(4) Development and evaluation of high-performance/low-power microprocessor architectures : The project has developed a couple of technologies good for high-performance/low-power microprocessors, such as (i) dynamic module selection technique utilizing multiple functional modules with different performance/power properties, (ii) realtime task scheduling algorithm for DVS (dynamic voltage scaling) processors, (iii) power-aware memory hierarchy, (iv) cache memory architectures adapting CCC (common case computation) principle to memory reference behavior.
(5) Development of applications of scalable system-LSI : The project has developed some scalable system-LSI applications, including (i) RSA cipher processor, (ii) MPEG2 AAC decoder, (iii) special-purpose processor for ERI (electron repulsion integral) calculations in computational chemistry programs. Less

Report

(3 results)
  • 2000 Annual Research Report   Final Research Report Summary
  • 1999 Annual Research Report
  • Research Products

    (35 results)

All Other

All Publications (35 results)

  • [Publications] K.Murakami: "Invited Talk : Current Status of PPRAM"Proc.6th International Conference on VLSI and CAD (ICVC'99). 266-276 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] H.Yasuura et al.: "System LSI Design Methods for Low Power LSIs"IEICE Transactions on Electronics. E83-C・2. 143-152 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] K.Inoue et al.: "A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection"IEICE Transactions on Electronics. E83-C・2. 186-194 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] K.Inoue et al.: "A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size"IEICE Transactions on Electronics. E83-C・11. 1716-1723 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] H.Yasuura: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals. E84-A・1. 91-97 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] K.Murakami et al.: "Trends in High-Performance, Low-Power Processor Architectures"IEICE Transactions on Electronics. E84-C・2. 131-138 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Inoue, K., Ishihara, T., and Murakami, K.: "Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption"Proc. of International Symposium on Low Power Electronics and Design (ISLPED'99). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Murakami, K.: "Invited Talk : Current Status of PPRAM"Proc. 6th International Conference on VLSI and CAD (ICVE'99). 266-276 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] OKuma, T., Ishihara, T., and Yasuura, H.: "Real-Time Task Scheduling for a Variable Voltage Processor"Proc. International Symposium on System Synthesis (ISSS'99). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hashimoto, K., Tomita, H., Inoue, K., Metsugi, K., Murakami, K., et al.: "MOE : A Special-Purpose Parallel Computer for High-Speed, Large Scale Molecular Orbital Calculation"Supercomputing (SC99). (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Yasuura, H.and Ishihara, T.: "System LSI Design Methods for Low Power LSIs"IEICE Transactions on Electronics. Vol.E83-C, No.2. 143-152 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Inoue, K., Ishihara, T., and Murakami, K.: "A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection"IEICE, Transactions on Electronics. Vol.E83-C, No.2. 186-194 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Ishihara, T., and Yasuura, H.: "A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors"Proc.Design Automation and Test in Europe (DATE2000). 617-622 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Sugihara, M., Date, H., and Yasuura, H.: "Analysis and Minimization of Test Time in a Combined BIST and External Test Approach"Proc.Design Automation and Test in Europe (DATE2000). 134-140 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hirose, K.and Yasuura, H.: "A Bus Delay Reduction Technique Considering Crosstalk"Proc.Design Automation and Test in Europe (DATE2000). 441-445 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Inoue, K., Kai, K., and Murakami, K.: "Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs"IEICE Transactions on Information and Systems. vol.E83-D, no. 5. 1048-1057 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Inoue, A., Ishihara, T., and Yasuura, H.: ""Flexible System LSI for Embedded Systems and Its Optimization Techniques""Journal of Design Automation for Embedded Systems, Kluwer Academic Publishers. vol.5, No.2. 179-205 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Hashimoto, K., Yamasaki, M., Tomita, H., Metsugi, K., and Murakami, K.: "PPRAM-Link : A New High-Speed Communication Interface Standard for Merged-DRAM/Logic System-on-a-Chip Architecture"SCI-Europe 2000. (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Yamashita, H., Yasuura, H., Eko, F.N., and Cao, Y.: "Variable Size Analysis and Validation of Computation Quality"Proc. Workshop on High-Level Design Validation and Test (HLDVT'00). 95-100 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Inoue, K., Kai, K., and Murakami, K.: "A High-Performace/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size"IEICE Transactions on Electronics. Vol.E83-C, No.11. 1716-1723 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Yasuura, H.: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.E84-A, No.1. 91-97 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Inoue, K.and Murakami, K.: "A Low-Power Instruction Cache Architecture Exploiting Program Execution Footprints"Proc.7th International Conference on High-Performance Computer Architecture. (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] Murakami, K.and Magoshi, H.: "Trends in High-Performance, Low-Power Processor Architectures"IEICE Transactions on Electronics. Vol.E84-C, No.2. 131-138 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2000 Final Research Report Summary
  • [Publications] 大隈孝憲 ほか: "可変電源電圧プロセッサに対するリアルタイムスケジューリング手法"電子情報通信学会論文誌. J83-C・6. 454-462 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] A.Inoue et al.: "Flexible System LSI for Embedded Systems and Its Optimization Techniques "Journal of Design Automation for Embedded Systems. 5・2. 179-205 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] H.Yamashita et al.: "Variable Size Analysis and Validation of Computation Quality"Proc.of Workshop on High-Level Design Validation and Test (HLDVT'00). 95-100 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] K.Inoue et al.: "A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size"IEICE Transactions on Electronics. E83-C・11. 1716-1723 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] H.Yasuura: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals. E84-A・1. 91-97 (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] K.Murakami et al.: "Trends in High-Performance, Low-Power Processor Architectures"IEICE Transactions on Electronics. E84-C・2. 131-138 (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 村上和彰: "情報処理最前線:システムLSIが創る新しいコンピュータ・アーキテクチャ"情報処理. 40・3. 303-307 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] F,N.Eko et al.: "A Cycle-Accurate Simulator for Soft-Core Processors"Proc,of 6th Confernce of Asia Pacific Chip Design Languages)APCHDL'99). 11-16 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] K,Murakami: "Invited Talk:Current Status of PPRAM"Proc.6th Int'l Conference on VLSI and CAD(ICVC'99). 266-276 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] T,Okuma et al.: "Real-Time Task Scheduling for a Variable Voltage Processor"Proc,of Int'1 Symposium on System Synthesis(ISSS'99). 24-29 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] H,Yasuura et al.: "System LSI Design Methods for Low Power LSIs"IEICE Transactions Electronics. E83-C・2. 143-152 (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] T,Ishihara et al.: "A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors"Proc,of Design Automation and Test in Europe (DATE2000). (印刷中). (2000)

    • Related Report
      1999 Annual Research Report

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Published: 1999-04-01   Modified: 2016-04-21  

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