| Project/Area Number |
11355015
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
KOYANAGI Mitsumasa Graduate School of Engineering, Tohoku University, Professor, 大学院・工学研究科, 教授 (60205531)
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| Co-Investigator(Kenkyū-buntansha) |
HANE Kazuhiro Graduate School of Engineering, Tohoku University, Professor, 大学院・工学研究科, 教授 (50164893)
ESASHI Masayoshi New Industry Creation Hatchery Center, Tohoku University, Professor, 未来科学技術共同研究センター, 教授 (20108468)
NAKAMURA Tadao Graduate School of Information Sciences, Tohoku University, Professor, 大学院・情報科学研究科, 教授 (80005454)
MIYAKAWA Nobuaki Fuji Xerox Co., LTD. Corporate Reserch Labs, Research Fellow, 総合研究所, 主幹研究員
KURINO Hiroyuki Graduate School of Engineering, Tohoku University, Assistant Professor, 大学院・工学研究科, 助教授 (70282093)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥32,740,000 (Direct Cost: ¥32,200,000、Indirect Cost: ¥540,000)
Fiscal Year 2001: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2000: ¥14,100,000 (Direct Cost: ¥14,100,000)
Fiscal Year 1999: ¥16,300,000 (Direct Cost: ¥16,300,000)
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| Keywords | Three Dimensional Integration / Parallel Processing / Wafer Level Integration / System on a Chip / Optical Interconnection / Memory / Semiconductor / LSI / ウェーハ張り合わせ技術 / ウエーハレベルインテグレーション / システムオンチップ / ウエーハ張り合わせ技術 / マイクロバンプ |
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| Research Abstract |
In this work, we have developed basic technologies for the wafer level parallel processing system using the cubid integration technology.
First of all, we developed the cubic integration technology to fabricate the three dimensional (3D) processor and the three dimensional (3D) shared memory. The 3D processor consists of the processor layer and the memory layers which are closely connected by vertical interconnections to solve the bus bottle neck between them. The 3D shared memory is a memory, in which several memory layers are stacked into one chip and closely connected each other by vertical interconnections. It can realize the parallel processing system without the bus bottle neck. We fabricated 3D processor and 3D shared memory and obtained excellent evaluation results. We also developed the optical interconnection technology to connect between chips in wafer level system. We could successfully demonstrate the optical data transfer operation between two chips on which a VCSEL and photodiodes are mounted.
We successfully demonstrate the possibility of wafer level parallel processing system using the cubic integration technology in this work.
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