| Project/Area Number |
11450125
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | HIROSHIMA UNIVERSITY |
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Principal Investigator |
YOKOYAMA Shin Research Center for Nanodevices and Systems, Hiroshima University, Professor, ナノデバイス・システム研究センター, 教授 (80144880)
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| Co-Investigator(Kenkyū-buntansha) |
NAKAJIMA Anri Research Center for Nanodevices and Systems, Hiroshima University, Professor, ナノデバイス・システム研究センター, 助教授 (70304459)
SHIBAHARA Kentaro Research Center for Nanodevices and Systems, Hiroshima University, Associate Professor, ナノデバイス・システム研究センター, 助教授 (50274139)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥10,600,000 (Direct Cost: ¥10,600,000)
Fiscal Year 2001: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 2000: ¥2,800,000 (Direct Cost: ¥2,800,000)
Fiscal Year 1999: ¥5,900,000 (Direct Cost: ¥5,900,000)
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| Keywords | Selective deposition of silicon / Atomic-layer deposition / Self-limiting mechanism / Dislane / Intermittent exposure method / Silicon narrow wire / Transistor / Coulomb blockade / 塩化水素脱離反応 / 2インチSiウェハ / ガスフローパターン / 金属触媒 / 光・熱触媒反応 / 多結晶シリコン / 微細トランジスタ / 低温電気伝導 / クーロン振動 / 非線形電気伝導 / シリコンドット / 低抵抗 / ジシラン熱分解 / シリコン窒化膜 / シリコン酸化膜 / 活性化エネルギー |
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| Research Abstract |
The purpose of this study is to develop a new method for fabrication of ultrasmall transistors, which is impossible by the conventional lithography method, by means of the selective atomic-layer deposition of silicon (Si). At the edge of the stacked layered structures consisting of different materials, if the selective deposition of Si occurs only on the specific material, the gate length of the MOS transistors can be controlled by the thickness of the deposited film. In this study, this method is developed. The summary of the obtained results is listed below.
1. The selective atomic-layer deposition method of silicon nitride is developed, which is the basis of this study.
2. The selective atomic-layer deposition method for Si is developed, in which the Si film is deposited only onto the silicon nitride and very small amount deposition on SiO_2, by means of the intermittent exposure of Si_2H_6 gas.
3. By using the above method, very narrow Si wires (21 nm wide and 28 nm thick) is fabricat
… More
ed. The resistivity of the Si wires is about 1/5 compared with that fabricated by the conventional method using lithography and dry etching.
4. Atomic-layer deposition method of Si with very smooth surface is developed by using the alternative supply of Si_2H_6 and SiCl_4, in which the deposition rate is two mono-layers per one deposition cycle.
5. As the preliminary study for the evaluation of the narrow Si wires, the polycrystalline (poly-) Si wires (minimum width of 95 nm and minimum thickness of 7 nm) were fabricated by using the low-pressure chemical vapor deposition of SiH_4, followed by the electron-beam lithography and dry etching. And the electrical characteristics were measured. As the result the Coulomb blockade effect was observed at low temperatures (5〜80 K) and the electronic conduction mechanism in the narrow poly-Si wires were proposed.
1. The current suppression phenomenon at the low-voltage region, which might be caused by the coulomb blockade effect, was observed for the Si narrow wires fabricated by the selective atomic-layer deposition. Less
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