• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

A Study on Delay and Function Test for Core-Based System LSIs

Research Project

Project/Area Number 11450143
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 電子デバイス・機器工学
Research InstitutionKyushu University

Principal Investigator

YASUURA Hiroto  Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 教授 (80135540)

Co-Investigator(Kenkyū-buntansha) MATSUNAGA Yuusuke  Kyushu University, Department of Computer Science and Communication Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
YAMASHITA Masafumi  Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 教授 (00135419)
MURAKAMI Kazuaki  Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 教授 (10200263)
SAWADA Sunao  Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 助手 (70235464)
IWAIHARA Mizuho  Kyoto University, Department of Social Informatics, Associate Professor, 大学院・情報学研究科, 助教授 (40253538)
伊達 博  , 財団法人・九州システム情報技術研究所, 研究員
廣瀬 啓  九州大学, 大学院・システム情報科学研究科, 日本学術振興会特別研究員
Project Period (FY) 1999 – 2001
Project Status Completed (Fiscal Year 2001)
Budget Amount *help
¥13,200,000 (Direct Cost: ¥13,200,000)
Fiscal Year 2001: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2000: ¥4,900,000 (Direct Cost: ¥4,900,000)
Fiscal Year 1999: ¥5,900,000 (Direct Cost: ¥5,900,000)
KeywordsCore-Based Design / System LSIs / Testing / Testing Time / BIST / External Testing / Performance Test / Dispersion of delay / コアベースシステム / CBET
Research Abstract

Recent significant advances in LSI technologies have been increasing the number of transistors on a chip dramatically. System designers can now build a large system on a single chip as a system-on-a-chip (SOC). They often use multiple pre-designed and pre-verified blocks to reduce the time required for design and verification. These cores include black-boxed cores whose details are unknown due to the protection of intellectual property (IP) information. The importance of testing the function and performance has been increasing as the LSI technologies have been increasing.
We proposed function and performance test methods for Core-Based System LSIs. We proposed a function test method named as CBET (Combination of BIST and External Test) scheme. We theoretically and experimentally validated that the CBET scheme can reduce much testing time. We also proposed a performance test method in which the delay time at a node is treated stochastically. This method can reduce extra margins of the delay time and therefore can estimate the performance for LSIs accurately.

Report

(4 results)
  • 2001 Annual Research Report   Final Research Report Summary
  • 2000 Annual Research Report
  • 1999 Annual Research Report
  • Research Products

    (17 results)

All Other

All Publications (17 results)

  • [Publications] 杉原 真, 安浦 寛人: "システムLSI時代における新テスト技術"情報処理学会論文誌. 第42巻第3号. 409-418 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] V.Iyenger, H.Date, M.Sugihara, K.Chakrabarty: "Hierarchical intellectual property protection using partially-mergeable cores"EICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. vol.E84-A, no.11. 2632-2638 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] M.Sugihara, H.Yasuura: "Optimization of test accesses with a combined BIST and external test scheme"EICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. vol.E84-A, no.11. 2731-2738 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] M. Sugihara, H. Yasuura: "A Novel Test Technique in the SOC Era"IPSJ Journal. Vol. 42, no. 3. 409-418 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] V. Iyengar, H. Date, M. Sugihara, and K. Chakrabarty: "Hierarchical intellectual property protection using partially-mergeable cores"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol. E84-A, no. 11. 2632-2638 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] M. Sugihara and H. Yasuura: "Optimization of test accesses with a combined BIST and external test scheme"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol. E84-A, no. 11. 2731-2738 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 杉原 真, 安浦 寛人: "システムLSI時代における新テスト技術"情報処理学会論文誌. 第42巻第3号. 409-418 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] V.Iyengar, H.Date, M.Sugihara, K.Chakrabarty: "Hierarchical intellectual property protection using partially-mergeable cores"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.E84-A, no.11. 2632-2638 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] M.Sugihara, H.Yasuura: "Optimization of test accesses with a combined BIST and external test scheme"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.E84-A, no.11. 2731-2738 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 杉原真,伊達博,安浦寛人: "BISTと外部テストの組合せでのテスト時間の分析とコア・ベース設計のテスト時間最小化"電子情報通信学会技術研究報告. VLD99-113. 39-46 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] M.Sugihara,H.Date,and H.Yasuura: "Analysis and Minimization of Test Time in a Combined BIST and External Test Approach"Proc. of Design Automation and Test in Europe (DATE2000). 134-140 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 溝口大介,安浦寛人: "遅延分布を用いたモデル化による性能見積もりに関する考察"2000年電子情報通信学会総合大会. A-3-14. 32 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 溝口大介,杉原真,安浦寛人: "ゲート遅延分布を用いた性能テスト手法"情報処理学会DAシンポジウム2000論文集. 173-178 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 杉原真,安浦寛人: "システムLSI時代における新テスト技術"情報処理学会論文誌. 第42巻3号. (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 杉原 真,他: "BISTと外部テストの組合せでのテスト時間の分析とコア・ベース設計のテスト時間最小化"電子情報通信学会技術研究報. (印刷中). (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] M.Sujigara,et al.: "Analysis and Minimization of Test Time in a Combined BIST and External Test Approach"Proc.of Design Automation and Test in Europe(DATE2000). (印刷中). (2000)

    • Related Report
      1999 Annual Research Report
  • [Publications] 溝口 大介,他: "遅延分布を用いたモデル化による性能見積もりに関する考察"2000年電子情報通信学会総合大会. (印刷中). (2000)

    • Related Report
      1999 Annual Research Report

URL: 

Published: 1999-04-01   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi