| Project/Area Number |
11450143
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Kyushu University |
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Principal Investigator |
YASUURA Hiroto Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
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| Co-Investigator(Kenkyū-buntansha) |
MATSUNAGA Yuusuke Kyushu University, Department of Computer Science and Communication Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
YAMASHITA Masafumi Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 教授 (00135419)
MURAKAMI Kazuaki Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 教授 (10200263)
SAWADA Sunao Kyushu University, Department of Computer Science and Communication Engineering, Professor, 大学院・システム情報科学研究院, 助手 (70235464)
IWAIHARA Mizuho Kyoto University, Department of Social Informatics, Associate Professor, 大学院・情報学研究科, 助教授 (40253538)
伊達 博 , 財団法人・九州システム情報技術研究所, 研究員
廣瀬 啓 九州大学, 大学院・システム情報科学研究科, 日本学術振興会特別研究員
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥13,200,000 (Direct Cost: ¥13,200,000)
Fiscal Year 2001: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2000: ¥4,900,000 (Direct Cost: ¥4,900,000)
Fiscal Year 1999: ¥5,900,000 (Direct Cost: ¥5,900,000)
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| Keywords | Core-Based Design / System LSIs / Testing / Testing Time / BIST / External Testing / Performance Test / Dispersion of delay / コアベースシステム / CBET |
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| Research Abstract |
Recent significant advances in LSI technologies have been increasing the number of transistors on a chip dramatically. System designers can now build a large system on a single chip as a system-on-a-chip (SOC). They often use multiple pre-designed and pre-verified blocks to reduce the time required for design and verification. These cores include black-boxed cores whose details are unknown due to the protection of intellectual property (IP) information. The importance of testing the function and performance has been increasing as the LSI technologies have been increasing.
We proposed function and performance test methods for Core-Based System LSIs. We proposed a function test method named as CBET (Combination of BIST and External Test) scheme. We theoretically and experimentally validated that the CBET scheme can reduce much testing time. We also proposed a performance test method in which the delay time at a node is treated stochastically. This method can reduce extra margins of the delay time and therefore can estimate the performance for LSIs accurately.
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