| Project/Area Number |
11480058
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
計算機科学
|
|---|
| Research Institution | Tohoku University |
|---|
Principal Investigator |
HIGUCHI Tatsuo Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (20005317)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
YUMINAKA Yasushi Gunma University, Faculty of Engineering, Lecturer, 工学部, 講師 (30272272)
AOKI Takafumi Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院・情報科学研究科, 助教授 (80241529)
|
|---|
| Project Period (FY) |
1999 – 2001
|
| Project Status |
Completed (Fiscal Year 2001)
|
| Budget Amount *help |
¥10,900,000 (Direct Cost: ¥10,900,000)
Fiscal Year 2001: ¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 2000: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 1999: ¥4,200,000 (Direct Cost: ¥4,200,000)
|
|---|
| Keywords | Hardware Algorithms / Integrated Circuits / Arithmetic Algorithms / Datapaths / Multiple-Valued Logic / Set-Valued Logic / Molecular Computers / Bio-Computers |
|---|
| Research Abstract |
The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. This research project is to investigate a possibility of overcoming the performance bottlenecks by employing a new computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project:
1. High-speed arithmetic algorithms using non-binary redundant number systems were developed and their performances were confirmed through experimental chip fabrications. Examples include (i) a radix-4 parallel divider chip, (ii) a radix-2-4-8 CORDIC processor chip, (iii) a configurable datapath chip using SW arithmetic, and (iv) a real/complex reconfigurable datapath chip using redundant complex arithmetic. Optimizing number representation for target applications makes possib
… More
le drastic reduction in computation time, power consumption and wiring complexity. Impacts of multiple-valued logic IC technology combined with redundant arithmetic algorithms were demonstrated through the design of field-programmable digital filter ICs. Also, new CAD techniques for designing beyond-binary circuits and systems were proposed.
2. A prototype of set-valued logic system, which uses pseudo-random sequences as information carriers, was designed and fabricated. The underlying principle of the fabricated system was extended to intra-chip CDMA communication techniques, which will be useful for implementing highly parallel computing architectures with reduced wiring complexity.
3. Techniques for computer-based simulation and analysis for enzyme transistor circuits were developed. These techniques were used to demonstrate some applications of molecular computing, including optimal path planning and image processing. The principle of wire-free circuit integration using artificial catalyst devices, such as enzyme transistors, was confirmed experimentally. Less
|
