| Project/Area Number |
11490028
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
広領域
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| Research Institution | Kumamoto University |
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Principal Investigator |
SUEYOSHI Toshinori Kumamoto University, Faculty of Engineering, Professor, 工学部, 教授 (00117136)
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| Co-Investigator(Kenkyū-buntansha) |
SHIROUZU Hiroshi Kyushu Matsushita Electric Co., LTD., Researcher, 技術本部・開発研究所, 研究員
SHIBAMURA Hidetomo Kumamoto University, Faculty of Engineering, Research Associate, 工学部, 助手 (10264136)
KUGA Morihiro Kumamoto University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (80243989)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥14,700,000 (Direct Cost: ¥14,700,000)
Fiscal Year 2001: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 2000: ¥4,000,000 (Direct Cost: ¥4,000,000)
Fiscal Year 1999: ¥8,500,000 (Direct Cost: ¥8,500,000)
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| Keywords | Reconfigurable Computing / Reconfigurable Logic / Programmable Logic / FPGA / Remote Reconfiguration / ラピッドプロトタイピング |
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| Research Abstract |
As mentioned in the research plan, we studied on next generation FPGA toward reconfigurable computing. The following are major results of the research.
1. Design and evaluation of a next generation FPGA
Requirements for a next generation FPGA toward reconfigurable computing were examined using commercial FPGAs. Moreover, basic architecture for a next generation FPGA were designed, and their quantitative evaluations were performed. In detail, area utilization, delay time, and implementation density were evaluated using practical circuits, and then a novel logic block suitable for next generation FPGA was proposed. The FPGA provides functions of multi-context, multi-grain/cluster, and configuration data cache was proposed. Furthermore, the following were made clear : the implementation density and the implementation efficiency were improved as compared with conventional logic block, and utilization of configuration data was reduced.
2. Building a development environment and supporting our p
… More
roposed next generation FPGA
A development environment of next generation FPGA for reconfigurable computing was built based on hardware/software co-design method. The multi-context extract tool and the technology-mapping tool were developed that effectively utilized various functions of the logic block for next generation FPGA we developed in this study.
3. Feasibility study on reconfigurable computing
The practical applications for multimedia use were developed, and the feasibility experiment was executed by industry-university co-operation. Moreover, the feasibility of software radio in the field of communication equipment was examined and the investigation using commercial FPGA was performed. From these results, the potential possibility of next generation FPGA for reconfigurable computing was confirmed. Besides, the device reconfiguration technology by remote control that utilized the merits of ISP function of IEEE1149.1 and the JAVA was developed, and its effectiveness was confirmed through the feasibility experiment. Less
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