• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits

Research Project

Project/Area Number 11555095
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 電子デバイス・機器工学
Research InstitutionKYOTO UNIVERSITY

Principal Investigator

ONODERA Hidetoshi  Graduate School of Informatics, Kyoto University, Professor, 情報学研究科, 教授 (80160927)

Co-Investigator(Kenkyū-buntansha) KANBARA Hiroyuki  The Advanced Software Technology and Mechatronics Research Institute of Kyoto, Senior Researcher, エレクトロニクス室長
HASHIMOTO Masanori  Graduate School of Informatics, Kyoto University, Research Associate, 情報学研究科, 助手 (80335207)
KOBAYASHI Kazutoshi  Graduate School of Informatics, Kyoto University, Associate Professor, 情報学研究科, 助教授 (70252476)
Project Period (FY) 1999 – 2001
Project Status Completed (Fiscal Year 2001)
Budget Amount *help
¥11,600,000 (Direct Cost: ¥11,600,000)
Fiscal Year 2001: ¥2,600,000 (Direct Cost: ¥2,600,000)
Fiscal Year 2000: ¥3,800,000 (Direct Cost: ¥3,800,000)
Fiscal Year 1999: ¥5,200,000 (Direct Cost: ¥5,200,000)
KeywordsManufacturing Variability / Statistical Analysis / Statistical Timing Analysis / Intra-Chip Variability / Inter-Chip Variability / VLSI / Hierarchical Design / Analog Circuit / 統計的解析 / ばらつき / 集積回路 / 歩留り最大化 / ロバスト設計 / 設計容易化技術 / 統計モデリング / モンテカルロ解析
Research Abstract

With steady improvement in LSI fabrication technology, variabilities of device characteristics, which are caused by fluctuation of manufacturing conditions, affect circuit performance considerably. The variabilities of device characteristics can not be completely eliminated by tuning fabrication processes, and hence a new design optimization methodology that can fundamentally consider the variabilities is necessary.
In this research, we develop four methods as fundamental and application techniques to analyze and optimize circuit performance statistically; 1) a modeling technique of the variabilities of device characteristics, 2) a statistical performance analysis method and a circuit optimization technique for large analog circuits, 3) a worst-case analysis method for digital circuits, 4) a statistical static timing analysis method and a performance optimization technique.
1) We develop a transformation method from the variabilities of physical parameters to the variabilities of device … More characteristics using an intermediate model. We devise two models that represent the variabilities; one is for systematic variabilities on a wafer, and the other is for local random variabilities. We also develop a measurement method for both types of the variabilities.
2) As for statistical performance analysis for large analog circuits, we develop a method that links the device characteristics variabilities to the system-level performance variabilities. This method builds a response surface for each hierarchy, and links the derived response surfaces. With the modeling techniques of 1), we can obtain the relationship between the variabilities of physical parameters and the system-level performance variabilities. We also develop an yield optimization method for hierarchical top-down design style.
3) We develop a delay calculation model called vector synthesis model. This model can calculate practical worst-case delay time with small computational costs. We also devise a method that instantly derives vector synthesis models of large circuits looking up pre-characterized reference tables.
4) We develop a statistical static timing analysis method. This method treats the uncertainties in delay calculation as statistical variables, and the derives a probability distribution at every node in a circuit. We then obtain the probability distribution of the circuit delay. We also develop a performance optimization method that minimizes the worst-case delay. Less

Report

(4 results)
  • 2001 Annual Research Report   Final Research Report Summary
  • 2000 Annual Research Report
  • 1999 Annual Research Report
  • Research Products

    (51 results)

All Other

All Publications (51 results)

  • [Publications] Masaki Kondo: "A Systematic and Physical Application of Multivariate Statistics to MOSFET I-V Models"Proc. International Workshop on Statistical Metrology. 34-37 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 藤田智弘: "現実的ワーストケースにおけるセルライブラリ遅延特性評価"情報処理学会DAシンポジウム'99論文集. 59-64 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "A Method for Linking Process-level Variability to system Performances"Proc. Asia and South Pacific Design Automation Conference. 547-551 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 藤田智弘: "ベクトル合成モデルによる集積回路遅延特性のワーストケース解析"情報処理学会論文誌. 41. 927-934 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis"Proc. ACM International Symposium on Physical Design. 111-116 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis"Proc. The Ninth Workshop on syntheses And System Integration of Mixed Technologies. 115-121 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 橋本昌宜: "静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法"第13回 回路とシステム(軽井沢)ワークショップ論文集. 137-142 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 藤田智弘: "アナログ集積回路の階層的歩留まり最適化手法"第13回 回路とシステム(軽井沢)ワークショップ論文集. 187-192 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fuijita: "Statistical Delay Calculation with Vector Synthesis Model"Proc. IEEE International Symposium on Circuits and Systems. V. 473-476 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Kenichi Okada: "Statistical Modeling of Device Characteristics with Systematic Fluctuation"Proc. IEEE International Symposium on circuits and Systems. II. 437-440 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 藤田智弘: "大規模集積回路の統計的遅延解析手法"情報処理学会DAシンポジウム2000論文集. 91-96 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "A Method for Linking Process-Level Variability to System Performances"IEICE Transactions on Fundamentals. 83-A. 2591-2599 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis"IEICE Transactions on Fundamentals. 83-A. 2558-2568 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing"Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. 34-37 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Takeo Yasuda: "A Dynamically Phase Adjusting PLL with a Variable Delay"Proc. Asia and South Pacific Design Automation Conference. 275-280 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Kenichi Okada: "Statistical Modeling of Device Characteristics with Systematic Variability"IEICE Trans. on Foundamentals. 84-A. 529-536 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "Increase in Delay Uncertainty by Performance Optimization"Proc. IEEE International Symposium on Circuits and Systems. V. 89-92 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance"IEICE Trans. on Fundamentals. E84-A. 727-734 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 岡田健一: "チップ内でのばらつきを考慮したトランジスタ特性ばらつきモデル化手法"情報処理学会DAシンポジウム2001論文集. 241-246 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Takeo Yasuda: "A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance"IEICE Trans. on Fundamentals. E84-A. 2793-2801 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masaki Kondo: "A Systematic and Physical Application of Multivariate Statistics to MOSFET I-V Models"Proc. International Workshop on Statistical Metrology. 34-37 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomhito Fujita: "A Method for Linking Process-level Variability to System Performances"Proc. Asia and South Pacific Design Automation Conference. 547-551 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "Statistical Delay Calculation with Vector Synthesis Model"IPSJ Trans. 41. 927-934 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A Performance Optimization Method by Gate Siz-ing using Statistical Static Timing Analysis"Proc. ACM International Symposium on Physical Design. 111-116 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoro: "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis"Proc. The Ninth Workshop on Synthesis And System Integration of Mixed Technologies. 115-121 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A Performance Optimization Method by Gate Sizing using Statistical Static Timing Analysis"Proc. The 13th Workshop on Circuits and Systems in Karuizawa. 137-142 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "A Hierarchical Statistical Optimization Method for Analog VLSI Circuits"Proc. The 13th Workshop on Circuits and Systems in Karuizawa. 187-192 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "Statistical Delay Calculation with Vector Synthesis Model"Proc, IEEE International Symposium on Circuits and Systems. Vol.V. 473-476 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Kenichi Okada: "Statistical Modeling of Device Characteristics with Systematic Fluctuation"Proc. IEEE International Symposium on Circuits and systems. Vol.II. 437-440 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "A Method of Statistical Dalay Calculation for VLSI"Proc.IPCJ DA Symposium2000. 91-96 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujira: "A Method for Linking Process-Level Variability to System Performances"IEICE Transactions on Fundamentals. Vol.83-A. 2591-2599 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A Performance Optimization Method by Gate Resizeing Based on Statistical Static Timing Analysis"IEICE Transactions on Fundamentals. Vol.83-A. 2558-2568 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "A statistical Delay- Uncertainty Analysis or the Circuits Path-Balanced by Gate/Transistor Sizing"Proc. ACM/IEEE TAU. 34-37 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Takeo Yasuda: "A Dynamically Phase Adjusting PLL with a Variable Delay"Proc. Asia and South Pacific Design Autmation Conference. 275-280 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Kenichi Okada: "Statistical modeling of Device characteristics with Systematic Variability"IEICE Trans. On Fundamentals. Vol.84-A. 529-536 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Masanori Hashimoto: "Increase in Delay Uncertainty by Performance Optimization"Proc. IEEE international Symposium on Circuits and Systems. Vol.V. 89-92 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Tomohiro Fujita: "A Hierarchical Statistical Optimization Method Driven by Constraint Generation Based on Mahalanobis' Distance"IEICE Trans, on Fundamentals. Vol.84-A. 727-734 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Kenichi Okada: "Statistical Modeling of Device Characteristics with IntraChip Variability"Proc. IPSJ DA Symposium2001. 241-246 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Takao.Yasuda: "A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance"IEICE Trans, on Fundamentals. Vol.E84-A. 2793-2801 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Takeo Yasuda: "A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance"IEICE Trans. on Fundamentals. E84-A. 2793-2801 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 岡田健一: "チップ内でのばらつきを考慮したトランジスタ特性ばらつきモデル化手法"情報処理学会DAシンポジウム2001論文集. 241-246 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Masanori Hashimoto: "Increase in Delay Uncertainty by Performance Optimization"Proc. IEEE International Symposium on Circuits and Systems. V. 89-92 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] K.Okada,H.Onodera: "Stastical Modeling of Device Characteristics with Systematic Variability"IEICE Transacions on Fundamentals. E84-A(2). 529-536 (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 藤田智弘,小野寺秀俊: "ベクトル合成モデルによる集積回路遅延特性のワーストケース解析"情報処理学会論文誌. 41(4). 927-934 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] T.Fujita,H.Onodera: "A Method for Linking Process-Level Variability to System Performances"IEICE Transaction Fundamental. E83-A(12). 2591-2599 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 藤田智弘,小野寺秀俊: "大規模集積回路の統計的遅延解析手法"情報処理学会DAシンポジウム2000論文集. 91-96 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 藤田智弘,小野寺秀俊: "アナログ集積回路の階層的歩留まり最適化手法"第13回回路とシステム軽井沢ワークショップ論文集. 187-192 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 藤田智弘,小野寺秀俊他: "システム特性の階層的統計解析手法"第12回 回路とシステム軽井沢ワークショップ論文集. 199-204 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 藤田智弘,小野寺秀俊他: "現実的ワーストケースにおけるセルライブラリ遅延特性の評価"情報処理学会DAシンポジウム'99論文集. 99. 59-64 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] M.Kondo,H.Onodera et.al.: "A Systematic and Physical Application of Multivariate Statistics to MOSFET I-V Models"Proc. 1999 4th International Workshop on Statistical Metrology. 34-37 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] T.Fujita,H.Onodera et.al.: "A Method for Linking Process-level Variability to System Performances"Proc of the Asia and South Pacific Design Automation Conference 2000. 547-551 (2000)

    • Related Report
      1999 Annual Research Report

URL: 

Published: 1999-04-01   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi