| Project/Area Number |
11558028
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku University |
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Principal Investigator |
HIGUCHI Tatsuo Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (20005317)
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| Co-Investigator(Kenkyū-buntansha) |
AOKI Takafumi Tohoku University, Graduate School of Information Sciences, Associate Professor, 大学院・情報科学研究科, 助教授 (80241529)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥11,800,000 (Direct Cost: ¥11,800,000)
Fiscal Year 2001: ¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 2000: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 1999: ¥5,300,000 (Direct Cost: ¥5,300,000)
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| Keywords | Hardware Algorithms / Integrated Circuits / VLSI / Datapaths / Arithmetic Algorithms / Redundant Number System / FPGA / Digital Signal Processing / デイジタル信号処理 |
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| Research Abstract |
Application specific ICs (ASICs) play an important role in present-day DSP technology. However, the ASIC technology requires significant time and cost for development, and is lacking the flexibility in design modification. The FPGA (Field-Programmable Gate Array) technology, on the other hand, attracts much attention recently due to its rapid prototyping capability, but it is difficult to apply FPGAs to high-performance systems. This research project is to develop configurable signal processors --- DSP-oriented FPGA architectures employing redundant arithmetic alogorithms for achieving both high-performance and programmabiligy. Listed below are major results of this project:
1. A configurable signal processor IC, that can implement high-frequency FIR filters with 10--100 MHz sampling rate, was developed. The test chip integrates redundant SW adders and can implement FIR filters of order up to 11. Assuming the use of state-of-the-art CMOS technology, the proposed architecture could be applied to QAM modulators/demodulators and format converters for digital TV applications, for example.
2. A configurable signal processor IC (for FIR filtering) using current-mode multiple-valued logic technology was developed, where 5-level bi-directional current signals are used for intra-chip communication. The use of multiple-valued logic makes possible to reduce the chip area by 50% and power consumption by 4-40%.
3. Various redundant arithmetic algorithms for DSP applications are systematically investigated. Also, new CAD techniques were developed for designing/verifying/synthesizing signal processors using redundant arithmetic algorithms.
4. A new fault-tolerant FPGA architecture that can detect hardware faults and reconfigure its architecture to recover the correct function was proposed for use in mission-critical applications.
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