| Project/Area Number |
11558032
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
HORIGUCHI Susumu Graduate School Information Science , Professor, 情報科学研究科, 教授 (60143012)
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| Co-Investigator(Kenkyū-buntansha) |
HAYASHI Ryouko JAIST, Information Science, Research Associate, 情報科学研究科, 助手 (30303332)
YAMAMORI Kunihito Miyazaki Univ, Faculty of Eng., Associate Prof., 工学部, 助教授 (50293395)
KOBAYASHI Hiroaki Tohoku Univ, Information Center, Professor, 情報シナジーセンター, 教授 (40205480)
INOGUCHI Yasushi JAIST, Information Center, Research Associate, 情報科学センター, 助手 (90293406)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥9,700,000 (Direct Cost: ¥9,700,000)
Fiscal Year 2001: ¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 2000: ¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 1999: ¥3,400,000 (Direct Cost: ¥3,400,000)
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| Keywords | fault tolerance / mesh array network / self-reconfiguration / wafer scale integration / FPGA / シフト・バイパス自律再構成 / VLSI・ULSI技術 / シラト・バイパス自律再構成 / VLSI再構成技術 / 自律再構成ネットワーク |
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| Research Abstract |
This research deals with the issue of reconfiguring network interconnection for mesh-connected processor arrays (mesh array) implemented in VLSI/WSI. For massively parallel systems, it is becoming necessary to develop self-reconfiguratopn architecture that can automatically reconfigure partially faulty systems. Many reconfiguration algorithms have been proposed to date, however, most of them are not suitable for the self-reconfiguration and little literature shows the hardware implementation of the architecture actually. In this research, we propose a hardware-oiented self- reconfiguration architecture based on simple schemes of column bypass and south directional rerouting, and show a hardware implementation of proposed architecture using FPGA. The main feature of the proposed self-reconfiguration architecture is that faulty processors are avoided by switchig mechanisum, which can be determined its desired function automatically using states of neighboring processors. Simulated result shows that the proposed self-reconfiguration architecture is that faulty processors are avoided by switching machanism, which can be determined its desired function automatically using states of neighboring processors. Simulated result shows that the proposed architecture achieves higher system yield than those of the previous archtectures in rectangular mesh arrays. We also implement the reconfiguration system in FPGA and have been discussed in performance of it. The hardware overhead of redundant circuits such as switches and control circuits shows less than 4 %, where hardware cost of a procesor, which includes a test circuit, is 50 Kgates.
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