| Project/Area Number |
11558035
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Fukuoka University |
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Principal Investigator |
MOSHUYAGA Vasily Faculty of Engineering, Assistant Prof., 工学部, 教授 (40243050)
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| Co-Investigator(Kenkyū-buntansha) |
ONODERA Hidetoshi Kyoto Univ., Graduate Sch. Of Informatics. Professor, 工学研究科, 教授 (80160927)
TSURUTA Naoyuki Faculty of Engineering, Assistant Prof., 工学部, 助教授 (60227478)
SUETSUGU Tadashi Faculty of Engineering, Assistant Prof., 工学部, 助教授 (60279255)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥7,900,000 (Direct Cost: ¥7,900,000)
Fiscal Year 2001: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2000: ¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1999: ¥3,500,000 (Direct Cost: ¥3,500,000)
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| Keywords | Processor / Architecture / Design Techniques / Low-Power / Date Reuse / Caches / Adiabatic Circuits / Energy Recovery / 論理合成 / 動画像圧縮 / 動き補償 / プロセッサアレー |
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| Research Abstract |
(a) Development of a Energy-Recovering Processor Architecture and its prototype chip implementation. We investigated a new concept of Energy-Recovering Processor Architecture and presented techniques for its implementation. Due to adiabatic charge-recovering and instruction and, data reuse, the architecture lowers the energy consumption by almost two orders of magnitude in comparison to the traditional processor design. To evaluate the architecture, a prototype LSI chip have been designed and fabricated.
(b) Development of Architectural Techniques for Reducing Transition Activity of Processing Hardware.Several new schemes to minimize switching activity of functional units, and register files by datadriven operand encoding, adaptive bit-width compression, operand transformation, bypassing, etc. have been proposed. Unlike conventional techniques, these methods can dynamically disable the hardware bits whose values remain unchanged, thus reducing unnecessary signal variations as much as ha]f without affecting the processing accuracy. The schemes are simple and easy in implementation.
(c) Development of Architectural Techniques for Variable Voltage Reduction of System Memory. New circuit techniques for adaptive voltage reduction in instruction issue queue, data and instruction caches have been proposed. In contrast to existing design approaches, the methods dynamically adjust the supply voltage to the level of instruction parallelism (issue queue) as well as the locality of accesses (caches), reducing the energy dissipation in these units by a factor of two without any impact on performance and very small area overhead.
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