Project/Area Number |
11640259
|
Research Category |
Grant-in-Aid for Scientific Research (C)
|
Allocation Type | Single-year Grants |
Section | 一般 |
Research Field |
素粒子・核・宇宙線
|
Research Institution | TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY |
Principal Investigator |
EMURA Tsuneo TOKYO UNIVERSITY OF AGURICULTURE AND TECHNOLOGY, TECHONOLOGY, PROFESSOR, 工学部, 教授 (40015053)
|
Co-Investigator(Kenkyū-buntansha) |
ARAI Yasuo HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION, INSTITUTE OF PARTICLE AND NUCLEAR STUDIES, ASSISTANT PROFESSOR, 素粒子原子核研究所, 助手 (90167990)
|
Project Period (FY) |
1999 – 2000
|
Project Status |
Completed (Fiscal Year 2000)
|
Budget Amount *help |
¥3,200,000 (Direct Cost: ¥3,200,000)
Fiscal Year 2000: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 1999: ¥2,100,000 (Direct Cost: ¥2,100,000)
|
Keywords | SOFTWARE TOOL / DIAGNOSING / VERILOG / TEST PATTERN DATA / BOUNDARY-SCAN STANNDARD / LARGE-SCALE INTEGRATED CIRCUIT / VERILOG SIMULATOR / BUFFER MEMORY / フロント・エンド・エレクトロニクス / カスコードアンプ / アナログサンプリング / COMS LSI / MOSトランジスタ / 回路シミュレーション / レイアウト設計 / デザインルール・チェック |
Research Abstract |
WE HAVE BEEN DEVELOPPING A SOFTWARE TOOL FOR DIAGNOSING VERILOG-DESIGNED LARGE -SCALE INTEGRATED CIRCUITS. THE TOOL IS BASED ON THE BOUNDARY-SCAN TEST STANDARD IEEE-1149.1. THE TEST PATTERN DATA ARE GENERATED BY THE VERILOG SIMULATOR THAT DESIGNS USER'S DIGITAL CIRCUITS. THE TEST DATA PATTERN IS TRANSLATED INTO A SET OF BOUNDARY-SCAN SIGNALS BY A LIBRARY OF BOUNDARY-SCAN TEST FUNCTIONS, WHICH IS DOWNLOADED INTO TESTING CIRCUITS THROUH A SERIAL OR PARALLEL PORT OF PC. WE USED THE TOOL TO TEST THE BUFFER MEMORY BULT IN OUR VERILOG-DESIGNED TDC AND COULD SEE THE TEST RESULT ON THE PC GRAPHICS.
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