| Project/Area Number |
11650316
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
SUGIURA Osamu Tokyo Institute of Tech., Fac. of Eng., Associate Prof., 工学部, 助教授 (10187643)
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| Project Period (FY) |
1999 – 2000
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 2000: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 1999: ¥2,300,000 (Direct Cost: ¥2,300,000)
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| Keywords | InSb / donor / sulfur / tin / p-n diode / self-alignment / MISFET / light-irradiating anneal / ドナードーピング / p-nダイオード / インジウムアンチモン / ドーピング |
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| Research Abstract |
Suitable source and drain structures for short channel InSb MISFETs were investigated. As donor impurity predeposition, Sulfur adsorption and thin tin film evaporation were examined. A light-irradiating anneal was used for diffusion and activation of the donor dopants. Rectify ratio of 10^4 was obtained by tin doping in p-type InSb substrates. Employing the doping method, InSb MISFETs were fabricated in self-alignment way. Without annealing after fabrication, the transistor did not show the transistor characteristics. However, after annealing with light-irradiation, the transistor was operated in n-channel mode. The mobility was a few cm^2/Vs, that is very small, and there was the large leakage current through drain junctions. Improving the process by reducing the annealing temperature and by reducing gate insulator thickness, transistors showed high mobility. The highest mobility was 1500 cm^2/Vs. This is explained by that alloy spikes were formed during high temperature annealing (300 ℃) and that the spike shunt the junction. Low temperature annealing (200 ℃) seems to be suitable for forming uniform junctions. The threshold voltage of transistors with normal mask patterns were lower than that of transistors with ring gate patterns. It means that gate electrodes protect InSb interface from light-irradiating. Because, thermally damaged MIS diodes commonly show negative voltage shift in C-V characteristics. Normal pattern transistors has the pass between source and dram which is not covered by gate electrode. The InSb interface under the pass was damaged during light-irradiating anneal and showed negative threshold voltages. This is the evidence that gate electrodes act as mask in the annealing process.
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