| Project/Area Number |
11650321
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Shinshu University |
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Principal Investigator |
KAMIMURA Kiichi Research Center for Educational Programs, Shinshu University Professor, 教育システム研究開発センター, 教授 (40113005)
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| Project Period (FY) |
1999 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2000: ¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 1999: ¥1,600,000 (Direct Cost: ¥1,600,000)
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| Keywords | Silicon Carbide / FET / MIS Interface / Contact Resistance / Hot Filament / サファイヤ基板 / 高温動作素子 |
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| Research Abstract |
Fundamental technologies have been established for fabrication of SiC FETs on sapphire substrate for high power and high temperature operation. During this research, it was also found that the boron films have excellent properties for a thermoelectric material used at high temperature.
In order to fabricate a high temperature, high power FET, it is important to obtain a gate insulating film with low interface state density and a high quality epitaxial semiconducting film. The sapphire is one of the excellent large diameter substrate for SiC epitaxial growth, but the difference of lattice constant may prevent the growth of high quality layer. In this work, Silicon-on-Sapphire (SOS) wafers were used as the substrates for SiC growth. The surface carbonization was effective to improve the quality of the SiC film. The leakage current to the substrate was expected to be reduced by using the sapphire as a substrate. A hot filament assisted method was effective to improve the quality of the film.
The source and drain electrode must have low contact resistance, together with high melting point. The electrical properties of metal/SiC contacts were investigated. The specific contact resistance was measured and discussed by transmission line model (TLM) method.
Both the MIS and MS structures were examined as the gate of SiC FET.The interface properties were controlled mainly by the surface condition of SiC and not so sensitive to the metal work function. MOS structure was fabricated with CVD deposited SiO_2 layer by using TEOS as a source material. Post deposition annealing was effective to reduce the interface state dendity. This method make it possible to eliminate the CO_2 formation, which resulted in poor interface characteristics in thermally grown SiO_2 on SiC sutructre.
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