| Project/Area Number |
11650358
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | SHIZUOKA INSTITUTE OF SCIENCE AND TECHNOLOGY |
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Principal Investigator |
TAYAMA Teruo SHIZUOKA INSTITUTE OF SCIENCE AND TECHNOLOGY (SIST), FACULTY OF ENGINEERING, PROFESSOR, 理工学部, 教授 (90267865)
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| Co-Investigator(Kenkyū-buntansha) |
MASUDA Tadashi SHIZUOKA INSTITUTE OF SCIENCE AND TECHNOLOGY (SIST), FACULTY OF ENGINEERING, PROFESSOR, 理工学部, 教授 (10106891)
NIWA Shohei SHIZUOKA INSTITUTE OF SCIENCE AND TECHNOLOGY (SIST), FACULTY OF ENGINEERING, PROFESSOR, 理工学部, 教授 (30023287)
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| Project Period (FY) |
1999 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥2,800,000 (Direct Cost: ¥2,800,000)
Fiscal Year 2001: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 2000: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1999: ¥1,300,000 (Direct Cost: ¥1,300,000)
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| Keywords | Image Processing / Rotary Encoder / Error Measurement / FPGA / Dataflow Machine / Functional Language / RISC Processor / Parallel Reduction / ロータリーエンコーダ / VHDL / リコンフィギャラブル / PCIバス / ロボット |
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| Research Abstract |
1. Real-Time Image Processing
To speed up image processing of autonomous mobile robots, a real-time image processing board for target detection by the pattern matching was developed. Since an image with a frame size of 256x256x8bits can be processed within 0.49ms, the target time of 33ms for single image processing is sufficiently cleared. Another Image processing board with 3 kinds of contours extraction circuit and 2 kinds of noise rejection circuit was also developed. The single image processing time became 5.2ms, twice as fast as that by software on a PC with a Pentium IV, 2.0-GHz processor. With this board, it succeeded in carrying out the dynamic reconfiguration.
2. Error Measurement Circuits for Rotary Encoder Calibration Systems
The whole circuit was designed by VHDL and implemented on a single-chip, 100,000-gate FPGA. With this chip, the time resolution and the limit frequency for the counter method were doubled. Using this board, a new rotary encoder calibration system which can calibrate all of the 225,000 angular graduations and has the angular resolution of ±0.001" and system Calibration accuracy of ±0.02" has been developed. This system was delivered in the National Institute of Advanced Industrial Science and Technology under the Ministry of Economy, Trade and Industry and was authorized as the National Standard in April, 2002.
3. Parallel Reduction Machine (PRM)
In order to realize a PRM which can handle a functional language with lazy evaluations and higher order functions, a design method based on a dataflow machine architecture was proposed. A new PRM board with two 100,000-gate FPGAs and 24 4M-bit SRAMs was developed and the complete operation of PRM was confirmed.
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