Hardware Synthesis of Communication Protocols in Real-Time LOTOS Language
| Project/Area Number |
11650379
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
情報通信工学
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| Research Institution | Osaka University |
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Principal Investigator |
HIGASHINO Teruo Graduate School of Eng.Sci. Osaka University Professor, 大学院・基礎工学研究科, 教授 (80173144)
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| Co-Investigator(Kenkyū-buntansha) |
OKANO Kozo Graduate School of Eng.Sci.Osaka University Assis.Prof., 大学院・基礎工学研究科, 講師 (70252632)
KITAMICHI Junji Cybermedia Center Osaka University Assis.Prof., サイバーメディアセンター, 講師 (20234271)
YASUMOTO Keiichi Shiga Univ.Fac.Economics Osaka University Assoc.Prof., 経済学部, 助教授 (40273396)
NAKATA Akio Graduate School of Eng.Sci.Osaka University Res. Assis., 大学院・基礎工学研究科, 助手 (60295839)
KITAJIMA Akira Graduate School of Eng.Sci.Osaka University Res. Assis., 大学院・基礎工学研究科, 助手 (00304030)
船曳 信生 大阪大学, 大学院・基礎工学研究科, 助教授 (70263225)
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| Project Period (FY) |
1999 – 2000
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| Project Status |
Completed (Fiscal Year 2000)
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| Budget Amount *help |
¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 2000: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 1999: ¥1,900,000 (Direct Cost: ¥1,900,000)
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| Keywords | LOTOS / Hardware Synthesis / Real-Time Systems / Concurrent Systems / FDTs / Communication Protocols / VHDL / Scheduling / 形式記述技法 / ハードウェア高位合成 / レジスタ転送レベル |
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| Research Abstract |
This research proposes a concurrent periodic EFSMs model and a technique to synthesize hardware circuits from specifications of real-time systems described in Real-Time LOTOS language. In the proposed model, data exchange by synchronous execution of the same events in multiple EFSMs can be specified as multi-way synchronization in LOTOS.The executable time range of each event can be given as a logical conjunction of linear inequalities of the execution time of its preceding events. Since each EFSM has some branches and some combination of branches of those EFSMs may not be executable because of their timing constraints, the proposed synthesis technique finds only executable combination of branches from a given specification and generates a scheduler for event sequences in each executable combination of branches. We have developed a tool to generate the corresponding RTL-level VHDL specification from a given specification, and generated circuits from some specifications such as a video playback chip. From those experiments, we have confirmed that the performance and size of the generated circuits are reasonable for practical use.
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Report
(3 results)
Research Products
(23 results)
