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Research on Branch Prediction and Speculative Execution

Research Project

Project/Area Number 11680351
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionNagoya University

Principal Investigator

SHIMODA Toshio  Nagoya University, School of Eng., Professor, 工学研究科, 教授 (60252251)

Co-Investigator(Kenkyū-buntansha) 小林 良太郎  名古屋大学, 工学研究科, 助手 (40324454)
安藤 秀樹  名古屋大学, 工学研究科, 助教授 (40293667)
Project Period (FY) 1999 – 2001
Project Status Completed (Fiscal Year 2001)
Budget Amount *help
¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 2001: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 2000: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 1999: ¥1,900,000 (Direct Cost: ¥1,900,000)
Keywordsbranch prediction / speculative execution / microprocessor / both-path execution / value prediction / 高速化
Research Abstract

To design a higher performance microprocessor in the future, it is important to study branch prediction and speculative execution. In this research we set a goal to attain higher performance by combining two branch prediction mechanisms. We describe the results in the following.
Both-path ExecutionWe have evaluated the Both-path execution mechanism using SPECint95. The processor with 8-instruction issue, 2-ported instruction cache, 4-ported data cache, and five contexts have showed performance improvement 20.5% at the maximum and 1 1.2% on the average compared with a conventional single-path execution. A new mechanism of branch prediction using branch filtering achieves a maximum of 8.1% performance improvement comparing to that of conventional decision mechanism.
Branch Prediction using Value PredictionThis mechanism predicts values of operand and opcode and then predicts branch direction. This can be used with the conventional branch prediction mechanism in hybrid. We evaluate this mec … More hanism by using SPECint95 and get the result of 2.55% improvement at the maximum and 0.84% improvement on the average about prediction accuracy compared with a conventional 4K-byte gshare mechanism. This means that a current superscaler processor can improve performance by a maximum of 5.95% and 2.43% on the average. When we use the processor with a deeper pipeline and wider instruction issue, the performance improvement is 14.1% at the maximum and 6.0% on the average.
A Branch Prediction schemes that reduces Destructive Aliasing Using Branch Direction BiasThis mechanism (named sgshre) divides the pattern history table into two parts, and maps branches with the same direction bias to only a single part of the table. Sgshare converts destructive aliasing into harmless aliasing. Our evaluation shows that sgshare achieves 0.05-0.89% better prediction accuracy than the conventional gshare. This contributes to the performance of a current superscaler processor by 7. 19% and that ofa future superscaler processor with a wider instruction issue and a deeper pipeline by 1 4.6%. Less

Report

(4 results)
  • 2001 Annual Research Report   Final Research Report Summary
  • 2000 Annual Research Report
  • 1999 Annual Research Report
  • Research Products

    (23 results)

All Other

All Publications (23 results)

  • [Publications] 片山清和 他5名: "値予測を利用した分岐予測機構"情報処理学会論文誌,ハイパフォーマンスコンピュートルティングシステム. Vol.42, No.SIG12. 22-36 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 片山清和 他2名: "両パス実行の性能評価と実行判定精度の改善"情報処理学会論文誌,ハイパフォーマンスコンピューティングシステム. Vol.42, No.SIG9. 106-118 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 小林良太郎 他4名: "2レベル表方式による分岐先バッファ"情報処理学会論文誌. 41・5. 1351-1359 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 野口良太 他4名: "遺伝的アルゴリズムを用いた分岐予測機構設計"計測自動制御学会論文集. 35・11. 1431-1437 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 野口良太 他4名: "分岐方向の偏りを利用し破壊的競合を低減する分岐予測方式"情報処理学会論文誌. 40・5. 2119-2131 (1999)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Kiyokazu Katayama, Satoru Toda, Kouji Nakmura,: "A branch prediction visa value prediction"Journal of Information Society of Japan. Vol. 42, No. SIG.12. 106-118 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Kiyokazu Katayama, Hideki Ando, and Toshio Shimada: "Performance evaluation of both-path execution and Improvement of execution decision accuracy"Journal of Information Society of Japan. Vol. 42, No. SIG.9. 22-36 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Ryotaro Kobayashi, Yuji Yamada, Hiedeki Ando, and: "A branch target buffer with a two-level table Scheme"IPSJ Journal. vol. 41, no.5. 1351-1359 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Ryouta Noguchi, Motoaki Matsuzakii, Ryotaro Kobayashi, Hiedeki.Ando, and Toshio Shimada: "Branch prediction design using genetic algorithm"Journal of the Society of Instrument and Control Engineers. Vol.36, No.11. 1431-1437

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] Ryouta Noguchi, Atsushi Mori, Ryotaro Kobayashi,: "A branch prediction scheme that reduces destructive aliasing using branch direction bias"Journal of Information Society of Japan. Vol.40, No.5. 2119-2131 (1999)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 片山清和 他2名: "両パス実行の性能評価と実行判定精度の改善"情報処理学会論文誌,ハイパフォーマンスコンピューティングシステム. Vol.42,No.SIG12. 22-36 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 片山清和 他5名: "値予測を利用した分岐予測機構"情報処理学会論文誌,ハイパフォーマンスコンピューティングシステム. Vol.42,No.SIG9. 106-118 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 松本潤一 他3名: "最近の値の局所性を利用するロード値予測手法"情報処理学会研究報告. 2002-ARC-146. 73-78 (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] 布施裕基,安藤秀樹,島田俊夫: "sgshare分岐予測機構における選択機構が予測性能に与える影響の評価"情報処理学会研究報告. 2001ARC・141. 53-58 (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 中村幸司,片山清和,布施裕基,安藤秀樹,島田俊夫: "値予測を用いた分岐予測機構の計算機性能に与える影響"情報処理学会研究報告. 2001ARC・141. 59-64 (2001)

    • Related Report
      2000 Annual Research Report
  • [Publications] 片山清和,安藤秀樹,島田俊夫: "分岐フィルタリングによる両パス実行性能の改善"2000年並列処理シンポジウムJSPP'2000. 253-260 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 戸田聡,布施裕基,片山清和,安藤秀樹,島田俊夫: "値予測を用いた分岐予測"2000年並列処理シンポジウムJSPP'2000. 237-244 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 小林良太郎,山田祐司,安藤秀樹,島田俊夫: "2レベル表方式による分岐先バッファ"情報処理学会論文誌. 41・5. 1351-1359 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 野口良太 他4名: "遺伝的アルゴリズムを用いた分岐予測機構設計"計測自動制御学会論文集. 35・11. 1496-1504 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 野口良太 他4名: "分岐方向の偏りを利用し破壊的競合を低減する分岐予測方式"情報処理学会論文誌. 40・5. 2119-2131 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Ryotaro Kobayashi 他4名: "An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism"Proceeding of 5th EUROMICRO Conference. 432-440 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] 山田祐司 他3名: "2レベル表構成の導入による分岐先バッファの容量削減"Proceeding of JSPP'99. 103-110 (1999)

    • Related Report
      1999 Annual Research Report
  • [Publications] Ryotaro Kobayashi 他3名: "COOL ChipsII '99"Proceeding of COOL ChipsII '99. 267-267 (1999)

    • Related Report
      1999 Annual Research Report

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Published: 1999-04-01   Modified: 2016-04-21  

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