| Project/Area Number |
11680356
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
計算機科学
|
|---|
| Research Institution | KYOTO UNIVERSITY |
|---|
Principal Investigator |
ONOYE Takao Kyoto University, Department of Communications and Computer Engineering, Associate Professor, 情報学研究科, 助教授 (60252590)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
FUJITA Gen Osaka University, Center of Advanced Research Projects, Research Associate, 先導的研究オープンセンター, 助手 (30304025)
IZUMI Tomonori Kyoto University, Department of Communications and Computer Engineering, Research Associate, 情報学研究科, 助手 (30303887)
MASAKI Toshihiro Osaka University, Information Technology Section Research Liaison Office, Lecturer, 工学研究科, 講師 (30294036)
|
|---|
| Project Period (FY) |
1999 – 2000
|
| Project Status |
Completed (Fiscal Year 2000)
|
| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2000: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 1999: ¥2,200,000 (Direct Cost: ¥2,200,000)
|
|---|
| Keywords | processor / embedded / interface / memory / media processing / video processing |
|---|
| Research Abstract |
In this project, high-speed and low-power processor architecture has been explored in order to facilitate media-enhanced high performance embedded systems. The research has been mainly carried out in the field of video codec systems.
First instruction execution of video codec algorithm over general purpose embedded processor is traced and analyzed in order to devise high speed functional unit architecture and its instructions in the processor. Then additional video and audio processing unit is introduced to ordinary existing memory accesing mechanism. As a result, media processing can be successfully executed in the processor system. In fact, as an embedded processor core, Xtensa configurable processor core of Tensilica Inc. is used in this project. A set of SIMD type parallel execution instructions for media processing are newly introduced to this processor. In addition, vector media processing mechanism is enabled to the Virtual Channel SDRAM of NEC by utilizing channel registers each with 2k bits.
Forthermore, we have deveped the following media processing basic technologies :
- low power VLSI implmentation of audio/video codec
- low memory bandwidth video encoder
- design of low power audio decoder
- hardware based algorithm of embedded encyption
- general purpose parallel processing architecture
|
