| Project/Area Number |
12044206
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| Research Category |
Grant-in-Aid for Scientific Research on Priority Areas
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| Allocation Type | Single-year Grants |
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| Review Section |
Science and Engineering
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| Research Institution | The University of Tokyo |
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Principal Investigator |
NANYA Takashi Research Center for Advanced Science and Technology, Professor, 先端科学技術研究センター, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
NAKAMURA Hiroshi Research Center for Advanced Science and Technology, Assoc-Professor, 先端科学技術研究センター, 助教授 (20212102)
寺田 浩詔 高知工科大学, 情報システム工学科, 教授 (80028985)
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| Project Period (FY) |
2000 – 2002
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| Project Status |
Completed (Fiscal Year 2003)
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| Budget Amount *help |
¥97,400,000 (Direct Cost: ¥97,400,000)
Fiscal Year 2002: ¥26,400,000 (Direct Cost: ¥26,400,000)
Fiscal Year 2001: ¥26,000,000 (Direct Cost: ¥26,000,000)
Fiscal Year 2000: ¥45,000,000 (Direct Cost: ¥45,000,000)
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| Keywords | Computer Architecture / Cascade ALU / Asynchronous system / CAD / SDI Model / AINOS / Memory system / Compile Technique / カスケードALUアーキテクチャ / メモリアーキテクチャ / SCIMA / 設計支援CADシステム / コンパイラ / 非同期式パイプライン / 多重並列演算方式 / 事象駆動原理 / 非同期式ライブラリ / ダブルバッファDDL / データフローアーキテクチャ / 自己タイミング制御方式 |
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| Research Abstract |
In this research, we proposed a cascaded ALU architecture for high-performance and real-time processing. Conventional high-performance superscalar processors suffer from increasing wire delays brought by semiconductor progress because their performance is limited by wire delay in the critical path. The Cascade ALU architecture, in which ALUs are cascaded dynamically to solve RAW dependencies between instructions, solves this problem by making the ALU part critical path. Because ALU speed is not limited by wire delays, the architecture can enjoy any further progress in device speed for an enhancement in processor performance. We have evaluated the performance and area size of the proposed cascade ALU. The results show that the cascade ALU architecture has a good performance scalability and little area penalty compared with current synchronous processors.
Since the delay of the Cascade ALU varies depending on executed instructions, asynchronous circuits are suitable for its implementation
… More
. Thus, we developed a CAD system for asynchronous VLSIs. This system, called AlNOS, accepts ordinary synchronous RTL descriptions in Verilog-HDL and generates asynchronous gate-level circuits based on SDI model. SDI is our novel delay model which assumes that the delay scaling variation between any two components is bounded. In the SDI model based design, high-speed operation can be achieved by utilizing delay information while preserving the robustness of circuits.
We also proposed a new memory architecture dedicated for high-performance and real-time processing. The memory architecture adopts software controlled memory (SCM) on the processor chip in addition to ordinary cache memory. The SCM and cache can be reconfigured dynamically depending on the characteristics of running applications. Since software can directly specify the data transfer between off-chip memory and SCM, the worst-case performance is strictly guaranteed which is favorable for real-time processing. In order to realize automatic software control, a compilation algorithm is developed and implemented. Less
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