| Project/Area Number |
12305020
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Tohoku University |
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Principal Investigator |
OHMI Tadahiro Tohoku University, New Industry Creation Hatchery Center, Professor, 未来科学技術共同研究センター, 教授 (20016463)
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| Co-Investigator(Kenkyū-buntansha) |
HIRAYAMA Masaki Tohoku University Graduate School of Engineering, Research Associate, 大学院・工学研究科, 助手 (70250701)
KOTANI Koji Tohoku University Graduate School of Engineering, Assistant Professor, 大学院・工学研究科, 助教授 (20250699)
SUGAWA Shigetoshi Tohoku University Graduate School of Engineering, Assistant Professor, 大学院・工学研究科, 助教授 (70321974)
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| Project Period (FY) |
2000 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥41,600,000 (Direct Cost: ¥37,100,000、Indirect Cost: ¥4,500,000)
Fiscal Year 2001: ¥19,500,000 (Direct Cost: ¥15,000,000、Indirect Cost: ¥4,500,000)
Fiscal Year 2000: ¥22,100,000 (Direct Cost: ¥22,100,000)
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| Keywords | LSI / Ta metal gate / gas-isolated-interconnects / mutual conductance / SOI / interface / trap level / low frequency noise / SOI / BPSG / 無水HF / 銅配線 / 金属基板 |
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| Research Abstract |
The purpose of this study is to establish ultra-high speed and high integrated giga scale integration technology that the operating frequency of integrated circuit has been accelerated up to 20 GHz though the maximum speed was so far thought less than 1 GHz in order to develop the ideal device structure, process and material to realize ultra acceleration and low electric power consumption of semiconductor integrated circuit. Because of a problem of Gate depletion, a metal gate should be needed. In this study, Ta metal gate technology characterized by the low-temperature process was developed. Especially, using perfect low-temperature processes below 450 ℃, Ta gate FD-SOI MNSFET using the direct silicon nitride as a gate insulator was made for the first time, and it was found that the sub-threshold coefficient had the ideal property of 66 mV/dec, and the interface property was very good. Furthermore, it is clarified that the mutual conductance of this MNSFET was higher than that of conv
… More
entional MOSFET at high gate bias region, and also the current drive capability was higher than that of conventional MOSFET.
The performance and reliability of the SOI device is strongly influenced to the electric activity defect of Si/SiO_2 (SOI/BOX) interface. In this study, the back gate bias - mutual conductance property of FD-SOI MOSFET was experimentally measured for the first time. Moreover, the formula of the surface potential in the thin film SOI MOS device in consideration of the potential drop between the SOI layer - substrate was newly derived, and also the energy level of the trap level for the SOI/BOX interface corresponding to a kink phenomenon and the high dose SIMOX substrate trap level and its density were clarified.
With miniaturization of a MOS device, the electric power-supply voltage must be reduced in order to improve the performance. Therefore, the reduction of the low frequency noise for improving a S/N ratio becomes very important from now on. In this research, it is clarified that the low frequency noise property of a partial depletion type SOI device was analyzed for the first time, and also the noise spectrum in SOI MOSFET adopted the ELTRAN wafer is purely equivalent to 1/f type in the pre-kink domain. Less
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