| Project/Area Number |
12358002
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Kyushu University |
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Principal Investigator |
MURAKAMI Kazuaki Kyushu Univ., Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (10200263)
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| Co-Investigator(Kenkyū-buntansha) |
IWAIHARA Mizuho Kyoto Univ., Grad. School of Informatics, Associate Professor, 大学院・情報学研究科, 助教授 (40253538)
MATSUNAGA Yusuke Kyushu Univ., Faculty of ISEE, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
YASUURA Hiroto Kyushu Univ., Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
TOMIYAMA Hiroyuki Institute of System and Information Technology, Researcher, 第1研究室, 研究員(研究職)
INOUE Sozo Kyushu Univ., Faculty of ISEE, Research Associate, 大学院・システム情報科学研究院, 助手 (90346825)
富山 宏之 (財)九州システム情報技術研究所, 第1研究室, 研究員
澤田 直 九州大学, 大学院・システム情報科学研究院, 助手 (70235464)
大隈 孝憲 九州大学, 大学院・システム情報科学府, 日本学術振興会特別研究員
伊達 博 (財)九州システム情報技術研究所, 第1研究室, 研究員
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| Project Period (FY) |
2000 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥43,000,000 (Direct Cost: ¥37,900,000、Indirect Cost: ¥5,100,000)
Fiscal Year 2002: ¥6,760,000 (Direct Cost: ¥5,200,000、Indirect Cost: ¥1,560,000)
Fiscal Year 2001: ¥15,340,000 (Direct Cost: ¥11,800,000、Indirect Cost: ¥3,540,000)
Fiscal Year 2000: ¥20,900,000 (Direct Cost: ¥20,900,000)
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| Keywords | system LSI / IP core / design methodology / design optimization / low power design / computer architecture / HW / SW codesign / dynamic optimization |
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| Research Abstract |
The objective of this research project is to develop architectures and design methodologies of customizable IP cores for system-LSI's. The project has performed the following research results.
(1) Development of customizable IP core architectures : The project has developed several customizable processors and co-processors as customizable IP cores, and design methodologies for these IP cores. The technologies developed include (I) customizable processors where the performance and energy consumption of their functional units can be (re)configured and optimized at either compile time or run time, (ii)customizable co-processors whose functionality and organization can be reconfigured at run time, (iii) online hardware synthesis technology which produces hardware configuration information for the customizable co-processors, and so on.
(2) Development of customizable memory core architectures : The project has developed several customizable memory cores and related technologies ; (I) customizing the instruction decoding for object programs, based on the statistical analysis on the appearance frequency of bit patterns of instructions, so that the power consumed for fetching instructions from a program ROM, (ii) customizing and reducing the number of tag lookups for instruction cache, based on the profile of instruction fetch addresses, so that the power consumed for checking the instruction cache tags, and so on.
(3) Development of customization techniques for variable-size datapath and memory-path : The project has developed some techniques for analyzing the dynamic ranges of variables in source programs, and then determining the size of datapath and memory-path so that tradeoff between the performance and power consumption can be achieved.
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