| Project/Area Number |
12450144
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Yokohama National University |
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Principal Investigator |
YOSHIKAWA Nobuyuki Yokohama National University, Faculty of Engineering, Associate Professor, 大学院・工学研究院, 助教授 (70202398)
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| Co-Investigator(Kenkyū-buntansha) |
KANEDA Hisayoshi Yokohama National University, Faculty of Engineering, Research Associate, 大学院・工学研究院, 助手 (30242382)
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| Project Period (FY) |
2000 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥15,000,000 (Direct Cost: ¥15,000,000)
Fiscal Year 2002: ¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 2001: ¥4,600,000 (Direct Cost: ¥4,600,000)
Fiscal Year 2000: ¥8,300,000 (Direct Cost: ¥8,300,000)
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| Keywords | single flux quantum / SFO circuits / superconductor / Josephson device / integrated circuit / binary decision diagram / superconductivity electronics / microprocessor / SFQ / 超伝導集積回路 / Josephson素子 / BDD / セルベース設計法 |
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| Research Abstract |
Single-flux-quantum (SFQ) logic circuits, which utilize an SFQ pulse in the superconducting circuits as a logical bit information, attract a great deal of attention recently because of their high-speed operating speed and low power dissipation compared with the semiconductor integrated circuits. Because the logical bit information in the SFQ circuits is represented by an SFQ, which is considered as a particle, we may build up a new type of logic operation system different from the conventional logic using me Boolean function.
The purpose of this study is to realize a single-quantum integrated system through the consideration of new SFQ logic circuits using a binary decision diagram (BDD), which is one kind of directional graphs.
In the research of 2001, we have optimized circuit parameters of the basic circuit cells for the BDD SFQ logic circuits and verified their operations. In 2002 we have designed and implemented the microprocessor components and investigated their functions in order to build a large-scale BDD SFQ logic circuit system. In 2003 we have designed the SFQ microprocessor prototype to investigate the feasibility of a large SFQ circuit system based on the asynchronous circuit design approach. The SFQ microprocessor designed is 8-bit bit-serial microprocessor having seven instructions. Its target clock frequency is 16 GHz. We have successfully confirmed the correct operations in all the circuit components, including register files, an ALU, a program counter and a controller.
These results show the feasibility of a large-scale SFQ logic circuit system as a high-end computing system in the next generation.
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