| Project/Area Number |
12450153
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
情報通信工学
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| Research Institution | Osaka University |
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Principal Investigator |
SHIRAKAWA Isao Osaka University, Department of Information Systems Engineering, Professor, 大学院・工学研究科, 教授 (10029100)
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| Co-Investigator(Kenkyū-buntansha) |
FUJITA Gen Osaka University, Center of Advanced Research Projects, Research Associate, 先導的研究オープンセンター, 助手 (30304025)
ONOYE Takao Kyoto University, Department of Communications and Computer, Associate Professor, 大学院・情報学研究科, 助教授 (60252590)
ISHIURA Nagisa Osaka University, Department of Information Systems Engineering, Associate Professor, 大学院・工学研究科, 助教授 (60193265)
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| Project Period (FY) |
2000 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥7,300,000 (Direct Cost: ¥7,300,000)
Fiscal Year 2001: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2000: ¥3,800,000 (Direct Cost: ¥3,800,000)
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| Keywords | discrete wavelet transform / VLSI / low power / retargetable compiler / ウエーブレット変換 / 画像圧縮 / MPEG-4 / JPEG2000 |
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| Research Abstract |
In this project, we developed VLSI architecture for video codec based on discrete wavelet transform. We developed a wavelet based algorithm for scalable still-image and video compression. The algorithm adopts a modified 2-D subband decomposition scheme in conjunction with a partial zerotree search for efficient Embedded Zerotree Wavelet coding. In spite of the performance inferiority to teh conventional DWT, the algorithm attains significant reduction of DWT memory requirements, enhancing a reasonable balance between implementation cost and image quality.
Furthermore, we implemented an MPEG-4 audio decoder, which is dedicated to portable audio appliances. Based on the results of sound quality evaluation, a low-power architecture is devised by means of frame-level pipeline and optimization of functional datapath. The proposed MPEG-4 audio decoder has been implemented with the use of 0.25 μm CMOS library, which integrates 30 k gates and dissipates 4.54 mW at 2.5 V supply.
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