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Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing

Research Project

Project/Area Number 12480064
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionTohoku University

Principal Investigator

KAMEYAMA MICHITAKA  Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)

Co-Investigator(Kenkyū-buntansha) HANYU TAKAHIRO  Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (40192702)
Project Period (FY) 2000 – 2002
Project Status Completed (Fiscal Year 2002)
Budget Amount *help
¥7,900,000 (Direct Cost: ¥7,900,000)
Fiscal Year 2002: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 2001: ¥2,800,000 (Direct Cost: ¥2,800,000)
Fiscal Year 2000: ¥2,900,000 (Direct Cost: ¥2,900,000)
KeywordsDual-Rail Current-Mode Multiple-Valued Integrated Circuit / Logic-In-Memory VLSI / Source-Coupled Logic / Fine-Grain Pipelinign / Ferro-Electric Device / Nonvolatile Logic-in-Mmemory / 電圧・電流ハイブリッドモード多値集積回路 / ドミノ理論 / パストランジスタ理論 / ソース結合形理論 / 多値VLSIプロセッサ / パイプライン処理 / ステレオビジョンプロセッサ
Research Abstract

The communication bottleneck between memories and logic modules is one of the most serious problems due to interconnection complexity in recent deep-submicron VLSI systems-on-a-chip. In the situation, high-performance and low-power VLSI circuit technologies suitable for multi-giga-hertz clock operations are expected to be developed. In this study, we proposed multiple-valued VLSI utilizing differential-pair circuit which has high-driving capability and ferroelectric-capacitor logic for low-power logic-in-memory VLSI.
1.Development of the highest performance multiple-valued VLSI
A novel-source-coupled logic style using multiple-valued signals is proposed for high-speed-low-power VLSI system. All the differential-pair circuits are driven by dual-rail signals, which we call "full source-coupled logic". Design and implementation results show that the performance of the full-source coupled logic circuit is very superior to the conventional multiple-valued source-coupled logic circuit. It is a useful circuit technology for multi-gigahertz and low-voltage operations.
2.Ferroelectic Logic-in-Memory Architecture
A functional pass gate and a nonvolatile logic-in-memory architecture are proposed for communication-bottleneck-free VLSI system. Transition of a remnant-polarization charge and capacitive coupling of a ferroelectric capacitor makes storage and switching functions which are merged into a ferroelectric capacitor. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric based circuitry to CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction in comparison with the equivalent CMOS implementation under 0.6μm ferroelecric/CMOS process.

Report

(4 results)
  • 2002 Annual Research Report   Final Research Report Summary
  • 2001 Annual Research Report
  • 2000 Annual Research Report
  • Research Products

    (80 results)

All Other

All Publications (80 results)

  • [Publications] 池司, 羽生貴弘, 亀山充隆: "2線式電流モード多値理論に基づくセルチェッキングVLSIシステム"電子情報通信学会論文誌C. J83-C, 4. 318-325 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameya: "DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage"IEEE Proceedings of the 30th International Symposium on Multiple-Valued Logic. 423-429 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: "Low-power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels"IEEE Proceedings of the Twenty-Ninth International Symposium on Multiple-Valued Logic. 382-387 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: "Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic"Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic. 438-447 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] 羽生貴弘, 亀山充隆: "2色2線式符号化に基づく非同期電流モード多値VLSIシステム"電子情報通信学会論誌C. Vol. J83-C, No.6. 463-470 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] 木村啓明, 羽生貴弘, 亀山充隆: "強誘電体デバイスを用いたロジックインメモリVLSIとその応用"電子情報通信学会論文誌C. Vol. J83-C, No.8. 749-756 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: "Integration of Asynchronous and Self-Checking Multiple-Valued Current-Mode Circuits Based on Dual-Rail Differential Logic"Proc.2000 IEEE Pacific Rim Int. Symposium on Dependable Computing. 27-33 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: "Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources"Proceedings of the 31st IEE International Symposium on Multiple-Valued Logic. 21-26 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran: "Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits"Proceedings of The 31st IEEE International Symposium on Multiple-Valued Logic. 167-172 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "Dynamic-Storage-Based Multiple-Valued Logic-in-Memory Circuit and Its Application"Proc. 2nd Korea-Japan Joint Symposium on Multiple-Valued Logic. 147-151 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] 亀山充隆: "未来情報社会を創る知能集積システム"東北大学大学院電気・情報系および電気通信研究所編:個性の輝くコミュニケーション-21世紀への夢-,東北大学出版会. 126-154 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: "Arithmetic-Oriented Logic-in-Memory VLSI Using Floating-Gate MOS Transistors"Multiple-Valued Logic. Vol.8(1). 33-51 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System"IEICE Trans. Electron. Vol. E85-C, No.2. 288-296 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu: "Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation"IEEE Int. Solid-State Circuits Conf. (ISSCC)Dig. Tech. Papers. 208-209 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition"Proc. of the 32nd IEEE International Symposium on Multiple-Valued Logic. 161-166 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: "Fully Source-Coupled Logic Based Multiple-Valued VLSI"Proc. of the 32nd IEEE Int. Symposium on Multiple-Valued Logic. 270-275 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu: "Ferroelectric-Based Functional Pass-Gate for Low-Power VLSI"IEEE Symp. VLSI Circuits, Dig. Tech. Papers. 196-199 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit"IEICE Trans. Electron. Vol. E85-C, No.10. 1814-1823 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "VLSI System Based on Ferroelectric Logic-in-Memory Architecture"2002 International Symposium on New Paradigm VLSI Computing. 60-65 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu: "Complementary Ferroelectric-Capacitor Logic and Its Application"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers. 160-161 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Tsukasa Ike, Takahiro Hanyu and Michitake Kameyama: "Self Checking VLSI System Based on Dual-Rail Multiple-Valued Current-Mode Logic"Trans.IEICE. J83-C,4. 318-325 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Hiromitsu Kimura and Michitaka Kameyama: "DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage"IEEE Proceedings of the 30th International Symposium on Multiple-Valued Logic. 423-429 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Tsukasa Ike and Michitaka Kameyama: "Low-power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels"IEEE Proceedings of the Twenty-Ninth International Symposium on Multiple-Valued Logic. 382-387 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Shunichi Kaeriyama, Takahiro Hanyu and Michitaka Kameyama: "Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic"Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic. 438-447 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu and Michitaka Kameyama: "Asynchronous Current-Mode Multiple-Valued VLSI System Based on Two-Color Two-Rail Coding"Trans.IEICE. J83-C, No.6. 463-470 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu and Michitaka Kameyama: "Logic-In-Memory VLSI Using Ferroelectric Devices and Its Application"Trans.IEICE. J83-C, No.8. 749-756 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Tsukasa Ike and Michitaka Kameyama: "Integration of Asynchronous and Self-Checking Multiple-Valued Current-Mode Circuits Based on Dual-Rail Differential Logic"Proc.2000 IEEE Pacific Rim Int. Symposium on Dependable Computing. 27-33 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Tsukasa Ike, Takahiro Hanyu and Michitaka Kameyama: "Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources"Proceedings of the 31st IEE International Symposium on Multiple-Valued Logic. 21-26 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro and Chotei Zukeran: "Multiple-Valued Mask-Programmbale Logic Array Using One-Transistor Universal-Literal Circuits"Proceedings of The 31st IEEE International Symposium on Multiple-Valued Logic. 167-172 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu and Michitaka Kameyama: "Dynamic-Storage-Based Multiple-Valued Logic-in-Memory Circuit and Its Application"Proc.2nd Korea-Japan Joint Symposium on Multiple-Valued Logic. 147-151 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Michitaka Kameyama: "Intelligent Integrated Systems for Creation of Future Information Society"Tohoku Univ.. Pub.. 126-154 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Shunichi Kaeriyama, Takahiro Hanyu and Michitaka Kameyama: "Arthmetic-Oriented Logic-in-Memory VLSI Using Floating-Gate MOS Transistors"Multiple-Valued Logic. 8(1). 33-51 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu and Michitaka Kameyama: "Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System"IEICE Trans. Electron. E85-C, No.2. 288-296 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura and Hidemi Takasu: "Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipelined VLSI Computation"IEEE Int. Solid-State Circuits Conf.(ISSCC)Dig.Tech.Papers. 208-209 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu and Michitaka Kameyama: "Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition"Proc.of the 32nd IEEE International Symposium on Multiple-Valued Logic. 161-166 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Tsukasa Ike, Takahiro Hanyu and Michitaka Kameyama: "Fully Source-Coupled Logic Based Multiple-Valued VLSI"Proc.of the 32nd IEEE Int. Symposium on Multiple-Valued Logic. 270-275 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura and Hidemi Takasu: "Ferroelectric-Based Functional Pass-Gate for Low-Power VLSI"IEEE Symp. VLSI Circuits, Dig.Tech.Papers. 196-199 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu and Michitaka Kameyama: "Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit"IEICE Trans. Electron.. E85-C, No.10. 1814-1823 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu and Michitaka Kameyama: "VLSI System Based on Ferroelectric Logic-in-Memory Architecture"2002 International Symposium on New Paradigm VLSI Computing. 60-65 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura and Hidemi Takasu: "Complementary Ferroelectric-Capacitor Logic and Its Application"IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers. 160-161 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] 山口 通智, 羽生貴弘, 亀山充隆: "適応的電源電圧制御に基づく低消費電力VLSIアーキテクチャ"電子情報通信学会総合大会. C-12-21. 103 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu: "Complementary Ferroelectric-Capacitor Logic and Its Application"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers. 160-161 (2003)

    • Related Report
      2002 Annual Research Report
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit"IEICE Trans. Electron.. Vol.E85-C, No.10. 1814-1823 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "VLSI System Based on Ferroelectric Logic-in-Memory Architecture"2002 International Symposium on New Paradigm VLSI Computing. 60-65 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 木村啓明, 羽生貴弘, 亀山充隆, 藤森敬和, 中村孝, 高須秀視: "強誘電体デバイスに基づくロジックインメモリVLSIの構成"信学技報. ICD2002-9. 7-12 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 木村啓明, 羽生貴弘, 亀山充隆, 藤森敬和, 中村孝, 高須秀視: "強誘電体デバイスを用いた機能パスゲートと低電力VLSIへの応用"電気学会 電子材料研究会資料. EMF-02-9〜18. 57-62 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 高橋知宏, 羽生貴弘, 亀山充隆: "多値双方向データ転送に基づく非同期VLSIシステム"多値論理研究ノート. Vol.25, No.5. 5-1-5-10 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 藤原誠, 亀山充隆: "超高基数Signed-Digit数高並列演算ハードウェアアルゴリズムとそのVLSI化"多値論理研究ノート. Vol.25, No.4. 5-1-5-10 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 池司, 羽生貴弘, 亀山充隆: "ソース結合形多値集積回路の高性能化と画像処理VLSIプロセッサヘの応用"信学技報. ICD2002-102. 45-50 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 亀山充隆, 羽生貴弘, 木村啓明: "強誘電体ロジックインメモリアーキテクチャに基づくシステムLSIの展望"信学技報. ICD2002-172. 47-52 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] T.Ike, T.Hanyu, M.Kameyama: "Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources"Proceedings of The 31st IEE International Symposium on Multiple-Valued Logic. 21-26 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] T.Hanyu, M.Kameyama, K.Shimabukuro, C.Zukeran: "Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits"Proceedings of The 31st IEEE International Symposium on Multiple-Valued Logic. 167-172 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: "Dynamic-Storage-Based Multiple-Valued Logic-in-Memory Circuit and Its Aplication"Proc.2nd Korea-Japan Joint Symposium on Multiple-Valued Logic. 147-151 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 南 正樹, 羽生 貴弘, 亀山 充隆: "ロジックインメモリアーキテクチャに基づくモルフォロジー画像処理用多値VLSIプロセッサ"多値技報. MVL01-11. 87-93 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 望月 孝祥, 羽生 貴弘, 亀山 充隆: "ダイナミック記憶に基づく2線式電流モード多値集積回路の高性能化とその応用"多値技報. MVL01-6. 42-49 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 古川 剛志, 羽生 貴弘, 亀山 充隆: "2線式電圧・電流ハイブリッドモード多値集積回路とそのロジックインメモリVLSIへの応用"多値技報. MVL01-7. 50-57 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 望月 孝祥, 羽生 貴弘, 亀山 充隆: "ソース結合形論理に基づく多値ドミノ集積回路の構成"信学技報. ICD2001-1 01,no.384. 61-66 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 藤原 誠, 亀山 充隆: "超高基数Signed-Digit数系に基づく高並列演算VLSIの構成"多値技報. MVL02-7,No.1. 46-55 (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] 金 尚賢, 羽生 貴弘, 亀山 充隆: "電圧・電流ハイブリッドモード多値集積回路とステレオビジョンVLSIブロセッサへの応用"多値技報. MVL02-8,No.1. 56-64 (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] 池 司, 羽生 貴弘, 亀山 充隆: "ソース結合形論理に基づく多値集積回路の構成"電子情報通信学会総合全国大会. C-12-19. (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 木村 啓明, 羽生 貴弘, 亀山 充隆: "ダイナミック記憶に基づく多値ロジックインメモリVLSI回路"電子情報通信学会総合全国大会. C-12-20. (2001)

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      2001 Annual Research Report
  • [Publications] 南 正樹, 羽生 貴弘, 亀山 充隆: "ロジックインメモリ構造モルフォロジー画像処理VLSIブロセッサの構成"計測自動制御学会学術講演会. 310A-1. (2001)

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  • [Publications] 池 司, 羽生 貴弘, 亀山 充隆: "高性能多値電流モード集積回路の設計"電子情報通信学会秋季全国大会. C-12-15. (2001)

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      2001 Annual Research Report
  • [Publications] 木村 啓明, 羽生 貴弘, 亀山 充隆: "ゲートレベルパイプライン用ロジックインメモリVLSIの構成"電子情報通信学会秋季全国大会. C-12-8. (2001)

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      2001 Annual Research Report
  • [Publications] 古川 剛志, 羽生 貴弘, 亀山 充隆: "ソース結合形回路を用いた多値ロジックインメモリVLSIの構成"電子情報通信学会秋季全国大会. C-12-9. (2001)

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      2001 Annual Research Report
  • [Publications] 池司,羽生貴弘,亀山充隆: "2線式電流モード多値論理に基づくセルフチェッキングVLSIシステム"電子情報通信学会論文誌C. Vol.J83-C,No.4. 318-325 (2000)

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  • [Publications] 羽生貴弘,亀山充隆: "2色2線式符号化に基づく非同期電流モード多値VLSIシステム"電子情報通信学会論文誌C. Vol.J83-C,No.6. 463-470 (2000)

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  • [Publications] 木村啓明,羽生貴弘,亀山充隆: "強誘電体デバイスを用いたロジックインメモリVLSIとその応用"電子情報通信学会論文誌C. Vol.J83-C,No.8. 749-756 (2000)

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  • [Publications] Takahiro Hanyu,Hiromitsu Kimura and Michitaka Kameyama: "DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSi with Charge Addition and Charge Storage"IEEE Proceedings of The 30th International Symposium on Multiple-Valued. 423-429 (2000)

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  • [Publications] Takahiro Hanyu,Tsukasa Ike,and Michitaka Kameyama: "Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels"IEEE Proceedings of The Twenty-Ninth International Symposium on Multiple-Valued. 382-387 (2000)

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  • [Publications] Shunichi Kaeriyama,Takahiro Hanyu and Michitaka Kameyama: "Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic"Proceedings of The 30th IEEE International Symposium on Multiple-Valued Logic. 438-443 (2000)

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  • [Publications] T.Hanyu,T.Ike and M.Kameyama: "Integration of Asynchronous and Self-Checking Multiple-Valued Current-Mode Circuits Based on"Proc.2000 IEEE Pacific Rim Int.Symposium on Dependable Computing. 27-33 (2000)

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  • [Publications] 池司,羽生貴弘,亀山充隆: "セルフチェッキング性を有する2線式電流モード多値集積回路と高性能算術演算VLSIへの応用"信学技報. FTS2000-3. 17-24 (2000)

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  • [Publications] 羽生貴弘,亀山充隆: "2色2線式電流モード多値非同期VLSIシステムとその応用"信学技法. FTS2000-2. 9-15 (2000)

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  • [Publications] 羽生貴弘,古川剛志,亀山充隆: "高並列性と高駆動能力性を有する電流モードロジックインメモリVLSIの構成"多値論理研究ノート. Vol.23,No.20. 20-1-20-10 (2000)

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  • [Publications] 木村啓明,羽生貴弘,亀山充隆: "局所演算性に基づくDynamic-Storage形Logic-In-Memory VLSIの構成"信学技報. ICD2000-135. 53-58 (2000)

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  • [Publications] 望月孝祥,羽生貴弘,亀山充隆: "ダイナミック記憶に基づく2線式電流モード多値集積回路の高性能化とその応用"多値技報. MVL01-6. 42-49 (2001)

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  • [Publications] 古川剛志,羽生貴弘,亀山充隆: "2線式電圧・電流ハイブリッドモード多値集積回路とそのロジックインメモリVLSIへの応用"多値技報. MVL01-7. 50-57 (2001)

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  • [Publications] 望月孝祥,羽生貴弘,亀山充隆: "複数電源電圧を用いた2線式電流モード多値集積回路に基づくパイプライン積和演算器"電気関係学会東北支部連合大会. 2H4. 288 (2000)

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  • [Publications] 池司,羽生貴弘,亀山充隆: "カレントミラーの高速化に基づく2線式多値電流モード集積回路の構成"電子情報通信学会秋季全国大会. C-12-20. 100 (2000)

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Published: 2000-04-01   Modified: 2016-04-21  

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