Grant-in-Aid for Scientific Research (B)
|Allocation Type||Single-year Grants|
|Research Institution||HIROSHIMA UNIVERSITY(2001)|
The University of Tokyo(2000)
KOIDE Tetsushi Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor, ナノデバイス・システム研究センター, 助教授 (30243596)
KITAGAWA Akio Kanazawa University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (10214785)
WAKABAYASHI Shin'ichi Hiroshima University, Graduate School of Engineering, Associate Professor, 大学院・工学研究科, 助教授 (50210860)
|Project Period (FY)
2000 – 2001
Completed(Fiscal Year 2001)
|Budget Amount *help
¥11,800,000 (Direct Cost : ¥11,800,000)
Fiscal Year 2001 : ¥3,200,000 (Direct Cost : ¥3,200,000)
Fiscal Year 2000 : ¥8,600,000 (Direct Cost : ¥8,600,000)
|Keywords||Deep-submicron / VLSI / ULSI CAD / Layout design / Floorplanning / Placement and routing / Genetic algorithm / Performance-driven / Buffer block planning / シミュレーティドアニーリング / ULSI|
In this research, we studied new layout design methods for layout design automation of deep-submicron VLSI chips so as to solve the problems considering the performance of circuits, hard/soft macros, and minimizing of design time.
(1) Performance-driven circuit partitioning method
An circuit partitioning algorithm under path delay constraints was proposed to optimize performance of circuit.
(2) Performance-driven floorplanning methods
For floorplanning design with hard/soft macros, we proposed a performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion and showed effectiveness of the method.
(3) Performance-driven placement method
A timing-driven standard cell placement method based on cell-clustering and the new placement model, that is, ameba model was proposed.
(4) Performance-driven routing methods
For multi-routing layer model, we proposed a timing-driven hierarchical global routing method using a Steiner tree generation algorithm with wire sizing and buffer insertion.
(5) Performance-driven hierarchical buffer-block planning method
We proposed a hierarchical buffer block planning method, which divides the chip area into global bins, taking timing constraint into account.
(6) Applications of an adaptive genetic algorithm to performance-driven layout design
We newly proposed an adaptive genetic algorithm based on elite degree and applied to the layout design problems. We also implemented the proposed GA as GA accelerator LSI chips to speed up the execution and got a prospect of high-speed execution of number 10 times for performance-driven layout methods.