| Project/Area Number |
12555102
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Hiroshima University |
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Principal Investigator |
SUNAMI Hideo Hiroshima University, Research Center for Nanodevices and Systems, Professor, ナノデバイス・システム研究センター, 教授 (10311804)
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| Co-Investigator(Kenkyū-buntansha) |
SHIBAHARA Kentaro Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor, ナノデバイス・システム研究センター, 助教授 (50274139)
横山 新 広島大学, ナノデバイス・システム研究センター, 教授 (80144880)
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| Project Period (FY) |
2000 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥13,000,000 (Direct Cost: ¥13,000,000)
Fiscal Year 2002: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 2001: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 2000: ¥9,800,000 (Direct Cost: ¥9,800,000)
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| Keywords | Beam channel / Field shield / Polysilicon fill / Enhanced oxidation / TMAH / SOI / Self-aligning / CMOS / 鞍型トランジスタ / 素子分離構造 / フィールド・シールド / ハンプ電流 / 電界集中 / 漏洩電流 / 鞍型ゲート / 局所酸化法 / 不純物濃度依存酸化 / プラズマドーピング / 側壁ドーピング |
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| Research Abstract |
The target of this research is to realize three-dimensional CMOS transistor consisting of two silicon beams of which side walls form an n-channel and a p-channel transistors. As the results, n-channel transistors have been successfully operated based on three major works cited below. Adding p-channel transistor to this n-channel, CNIOS transistor can be formed
(1) Field shield device isolation technique :
To suppress degradation of sub-threshold characteristics due to electric filed concentration at the beam edge, a novel isolation technique is developed utilizing impurity enhanced oxidation with self-aligned polysilicon fill
(2) Corrugated n-channel transistor with 2-μm channel length :
An n-channel transistor with 1-μm high and 50-nm multiple silicon beams is realized utilizing an inisotropic etchant of tetra methyl ammonium hydroxide, TMAH.A transistor with 2-μm channel length and 31 beams outperforms conventional planar transistor by 5 times in drivability
(3) Beam channel n-MOS transistor with 0.2-μm channel length :
Beams of 1 μm in height and 50 nm in width are formed on silicon-on-insulator, SOI using dry etching. An n-MOS transistor with 0.2-μm channel length is successfully operated with newly developed self-aligned gate insulation technique utilizing impurity enhanced oxidation
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