| Project/Area Number |
12558024
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 展開研究 |
|---|
| Research Field |
計算機科学
|
|---|
| Research Institution | Tohoku University |
|---|
Principal Investigator |
AOKI Takafumi Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (80241529)
|
|---|
| Project Period (FY) |
2000 – 2002
|
| Project Status |
Completed (Fiscal Year 2002)
|
| Budget Amount *help |
¥5,200,000 (Direct Cost: ¥5,200,000)
Fiscal Year 2002: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 2001: ¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 2000: ¥2,200,000 (Direct Cost: ¥2,200,000)
|
|---|
| Keywords | Evolutionary Computation / Genetic Algorithms / Genetic Programming / Cluster Computing / Parallel Processing / Hardware Algorithms / VLSI / Logic Synthesis / クラスタ / 算術アルゴリズム / 進化的計算 / CAD / VLSI設計技術 / 並列計算機 |
|---|
| Research Abstract |
This research project is to investigate a possibility of designing arithmetic circuits automatically by employing a new evolutionary optimization, technique called Evolutionary Graph Generation(EGG). Listed below are major results of this project :
1. A parallel EGG system based on the coarse-grained model of parallel processing was developed for synthesizing arithmetic circuits efficiently.
2. An experimental 11-node Linux PC cluster was built for implementing the parallel EGG system.
3. A new version of EGG system that can be used to synthesize heterogeneous networks of various different components such as analog/digital-mixed components was proposed. The new EGG system with terminal-color constraint was proved to be useful for reducing search space of possible circuit configurations.
4. The performance of the developed EGG system was evaluated through a set of experiments for synthesizing various arithmetic circuits including constant-coefficient multipliers, constant-coefficient multiply-adders, bit-serial adders, bit-serial constant-coefficient multipliers, bit-seril constant-coefficient multiply-adders and current-mode logic circuits. Our observation shows that EGG is suitable for circuit design problems that can be handled by circuit graphs with up to 50 nodes.
5. A new evolutionary operation called "transmigration" was investigated for accelerating EGG's evolution process.
Further investigations on a general-purpose EGG framework for practical applications are being left as future research subjects.
|
