| Project/Area Number |
12558029
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Kyushu University |
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Principal Investigator |
YASUURA Hiroto Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
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| Co-Investigator(Kenkyū-buntansha) |
IWAIHARA Mizuho Kyoto University, Graduate School of Informatics, Associate Professor, 大学院・情報科学研究科, 助教授 (40253538)
MATSUNAGA Yusuke Kyushu University, Graduate School of Information Science and Electrical Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
MURAKAMI Kazuaki Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (10200263)
OKUMA Takanori Kyushu University, Graduate School of Information Science and Electrical Engineering, JSPS DC1, 大学院・システム情報科学研究院, 日本学術振興会特別研究員
SAWADA Sunao Kyushu University, Graduate School of Information Science and Electrical Engineering, Research Associate, 大学院・システム情報科学研究院, 助手 (70235464)
伊達 博 , 財団法人・九州システム情報技術研究所, 研究員
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| Project Period (FY) |
2000 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥13,300,000 (Direct Cost: ¥13,300,000)
Fiscal Year 2001: ¥5,400,000 (Direct Cost: ¥5,400,000)
Fiscal Year 2000: ¥7,900,000 (Direct Cost: ¥7,900,000)
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| Keywords | Low Energy / System on a Chip / Variable Voltage / Embedded System / System Software / Processor / Architecture / Memory |
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| Research Abstract |
This work discusses some basic techniques of software for variable-voltage processors in order to realize low-energy design, together with modeling techniques and evaluations of their potential benefits by simulation. Details are listed as follows :
1) A task scheduling technique for a real-time system with a variable-voltage processor, by which supply voltage is changed dynamically, is presented.
2) A platform for datapath width optimization of soft-core processors is built and the presented methodology of datapath optimization is evaluated by using MPEG AAC decoder. In addition, an energy minimization methodology using datapath width optimization is proposed. To find the optimized datapath width for a given application in the early phase of designs, an effective bitwidth and access frequency of variables based performance estimation technique is also developed. A low-energy memory design technique is presented as well.
3) A new datapath width optimization methodology considering computation precision targeting area and power reduction is presented.
4) A power reduction technique by reducing switching of redundant bit is presented, here effective bit line on data bus is called active bit, the other bit is called redundant bit.
5) A cost model for SoC (System on a Chip), in which each cost as a parameter is presented, and a design method by market scale and number of products is also presented.
6) High-performance/low power cache architectures with variable cache-line size for merged DRAM/Logic LSIs are presented ; in addition, a low-power instruction cache architecture exploiting program execution footprints is presented.
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