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The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption

Research Project

Project/Area Number 12558029
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionKyushu University

Principal Investigator

YASUURA Hiroto  Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (80135540)

Co-Investigator(Kenkyū-buntansha) IWAIHARA Mizuho  Kyoto University, Graduate School of Informatics, Associate Professor, 大学院・情報科学研究科, 助教授 (40253538)
MATSUNAGA Yusuke  Kyushu University, Graduate School of Information Science and Electrical Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
MURAKAMI Kazuaki  Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (10200263)
OKUMA Takanori  Kyushu University, Graduate School of Information Science and Electrical Engineering, JSPS DC1, 大学院・システム情報科学研究院, 日本学術振興会特別研究員
SAWADA Sunao  Kyushu University, Graduate School of Information Science and Electrical Engineering, Research Associate, 大学院・システム情報科学研究院, 助手 (70235464)
伊達 博  , 財団法人・九州システム情報技術研究所, 研究員
Project Period (FY) 2000 – 2001
Project Status Completed (Fiscal Year 2001)
Budget Amount *help
¥13,300,000 (Direct Cost: ¥13,300,000)
Fiscal Year 2001: ¥5,400,000 (Direct Cost: ¥5,400,000)
Fiscal Year 2000: ¥7,900,000 (Direct Cost: ¥7,900,000)
KeywordsLow Energy / System on a Chip / Variable Voltage / Embedded System / System Software / Processor / Architecture / Memory
Research Abstract

This work discusses some basic techniques of software for variable-voltage processors in order to realize low-energy design, together with modeling techniques and evaluations of their potential benefits by simulation. Details are listed as follows :
1) A task scheduling technique for a real-time system with a variable-voltage processor, by which supply voltage is changed dynamically, is presented.
2) A platform for datapath width optimization of soft-core processors is built and the presented methodology of datapath optimization is evaluated by using MPEG AAC decoder. In addition, an energy minimization methodology using datapath width optimization is proposed. To find the optimized datapath width for a given application in the early phase of designs, an effective bitwidth and access frequency of variables based performance estimation technique is also developed. A low-energy memory design technique is presented as well.
3) A new datapath width optimization methodology considering computation precision targeting area and power reduction is presented.
4) A power reduction technique by reducing switching of redundant bit is presented, here effective bit line on data bus is called active bit, the other bit is called redundant bit.
5) A cost model for SoC (System on a Chip), in which each cost as a parameter is presented, and a design method by market scale and number of products is also presented.
6) High-performance/low power cache architectures with variable cache-line size for merged DRAM/Logic LSIs are presented ; in addition, a low-power instruction cache architecture exploiting program execution footprints is presented.

Report

(3 results)
  • 2001 Annual Research Report   Final Research Report Summary
  • 2000 Annual Research Report
  • Research Products

    (23 results)

All Other

All Publications (23 results)

  • [Publications] K.Inoue, K.Kai, K.Murakami: "Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs"IEICE Transactions on Information and Systems. Vol.E83D. 1048-1057 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 大隈孝憲, 石原亨, 安浦寛人: "可変電源電圧プロセッサに対するリアルタイムスケジューリング手法"電子情報通信学会論文誌. Vol.J83C. 454-462 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] A.Inoue, T.Ishihara, H.Yasuura: "Flexible System LSI for Embedded System and Its Optimization Techniques"Journal of Design Automation for Embedded Systems. Vol.5,No.2. 179-205 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] K.Inoue, K.Kai, K.Murakami: "High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size"IEICE Transactions on Electronics. Vol.E83-C2. 1716-1723 (2000)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] H.Yasuura: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals on Electronics. Vol.E84-A2. 91-97 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] T.Okuma, T.Ishihara, H.Yasuura: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers. Vol.18No.2. 32-41 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] K. Inoue, K. Kai, and K. Murakami: "Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs"IEICE Transactions on Information and Systems. Vol. E83-D. 1048-1057 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] T. Okuma, T. Ishihara, and H. Yasuura: "Real-Time Task Scheduling for a Variable Voltage Processor (in Japanese)"IEICE Transactions on Electronics. Vol. J83-C. 454-462 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] A. Inoue, T. Ishihara, and H. Yasuura: "Flexible System LSI for Embedded System and Its Optimizatioin Techniques"Journal of Design Automation for Embedded Systems. Vol. 5, No. 2. 179-205 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] K. Inoue, K. Kai, and K. Murakami: "A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size"IEICE Transactions on Electronics. Vol. E83-C. 1716-1723 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] H. Yasuura: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals of Electronics. Vol. E84-A. 91-97 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] T. Okuma, T. Ishihara, and H. Yasuura: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers. Vol. 18, No. 2. 32-41 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2001 Final Research Report Summary
  • [Publications] 井上弘士, 石原亨, 甲斐康司, 村上和彰: "DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ"情報処理学会論文誌. 第42巻第3号. 419-431 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] T.Okuma, T.Ishihara, H.Yasuura: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers. Vol.18No.2. 32-41 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Y.Cao, H.Yasuura: "A System-level Energy Minimization Approach Using Datapath Width Optimization"Proceeding of ISLPED'01. 231-236 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] T.Okuma, H.Yasuura: "Low-Energy Real-Time OS Using Voltage Scheduling Algorithm for Variable Voltage Processors"Proceeding of SASIMI'01. 340-345 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Y.Cao, H.Yasuura: "Video Quality Modeling for Quality-driven Design"Proceeding of SASIMI'01. 86-92 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 室山真徳, 兵頭章彦, 大隈孝憲, 安浦寛人: "アクティブビットを考慮したバスの低消費電力化手法"電子情報通信学会技術研究報告. (印刷中). (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] K.Inoue,K.Kai,and K.Murakami: "Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs"IEICE Transactions on Information and Systems. vol.E83-D,no.5. 1048-1057 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] 大隈孝憲,石原亨,安浦寛人: "可変電源電圧プロセッサに対するリアルタイムスケジューリング手法"電子情報通信学会論文誌. Vol.J83-C. 454-462 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] K.Inoue,K.Kai,and K.Murakami: "A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size"IEICE Transactions on Electronics. Vol.E83-C,No.11. 1716-1723 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] H.Yamashita,H.Yasuura,F.N.Eko,and C.Yun: "Variable Size Analysis and Validation of Computation Quality"Proc.of Workshop on High-Level Design Validation and Test (HLDVT'00). 95-100 (2000)

    • Related Report
      2000 Annual Research Report
  • [Publications] H.Yasuura: "Towards the System LSI Design Technology"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.E84-A,No.1. 91-97 (2001)

    • Related Report
      2000 Annual Research Report

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Published: 2000-04-01   Modified: 2016-04-21  

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