| Budget Amount *help |
¥7,700,000 (Direct Cost: ¥7,700,000)
Fiscal Year 2002: ¥1,600,000 (Direct Cost: ¥1,600,000)
Fiscal Year 2001: ¥1,600,000 (Direct Cost: ¥1,600,000)
Fiscal Year 2000: ¥4,500,000 (Direct Cost: ¥4,500,000)
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| Research Abstract |
1 A Hardware Simulation Engine Based on Decision Diagram
A hardware logic simulation engine based on decision diagrams is presented. For the data structure of the engine, we propose PMDDs (Paged reduced ordered Multi-valued Decision Diagrams). A unit of this engine consists of memory (RAMs) and control circuits: RAMs store the PMDD data, and the control circuits trace the edges according to the input vectors. The engine consists of several units, and is accelerated by pipelining. Experimental results using a prototype are shown.
2. Evaluation of Multiple-Output Logic Functions using Decision Diagrams
This part shows four different methods to evaluate multiple-output logic functions using decision diagrams: Shared BDD (SBDD), Multi-Terminal BDD (MTBDD), BDD for characteristic functions (CF), and BDDs for Encoded Characteristic Function for Non-zero outputs (ECFNs). Methods to compute average evaluation time for each type of decision diagrams are presented. By experimental analysis using be
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nchmark functions, the number of nodes and average evaluation time are compared. Our results show that BDDs for ECFNs outperforms MTBDDs, BDDs for CFs, and SBDDs with respect to both number of nodes and computation time. The sizes of BDDs for ECFNs are smaller than for MTBDDs, BDDs for CFs, and SBDDs.
3. A Cascade Realization of Multiple-Output Function for Reconfigurable Hardware
A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of lookup tables (LUTs). And finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA.
4. Encoding of Boolean Functions and Its Application to LUT Cascade Synthesis
The problem or encoding arises in several areas of logic synthesis. Due to the nature of this problem, it is often difficult to systematically explore the space of all feasible encodings to find an optimal one. In this part, we show that when the objects to be encoded are Boolean functions, it is possible to formulate and solve problem optimally. We present a general approach to the encoding problem with one or more code-bit functions having some desirable properties. The method allows for an efficient implementation using branch-and-bound procedure coupled with specialized BDD operators. The proposed approach was used to synthesize lookup table (LUT) cascades implementing Boolean functions. Experimental results show that it finds optimal solutions for complex encoding problems in less than a second of CPU time.
5. Logic Synthesis of LUT Cascades with Limited Rails
Programmable LUT cascades are used to evaluate multi-output Boolean functions. This part shows several representations of multi-output functions and introduces a new decomposition algorithm applicable to these representations. The algorithm produces LUT cascades with the limited number of rails, which leads to significantly faster circuits and applicability to large designs. The experiment shows that the proposed algorithm performs well on benchmark functions.
6. Average Path Length as a Paradigm for the Fast Evaluation of Functions Represented by Binary Decision Diagrams
This part focuses on the average path length (APL) of BDD's for switching functions. APL is a metric for the time it takes to evaluate the function by a computer program. We derive the APL for the AND, OR, parity, carry-out, comparison, threshold symmetric, and majority functions. We also consider the average of the APL for various classes of functions, including symmetric, threshold symmetric, and unate cascade. For symmetric functions, we show the average APL is close to the maximum path length, n, the number of variables. We show there are exactly two functions, the parity functions, that achieve the upper bound, n, on the APL for BDD's over all functions dependent on n variables. All other functions have an APL strictly less than n. We show that the APL of BDD's over all functions dependent on n variables is bounded below by 2 - 2^<-(n-1)>. The set of functions that achieves this small value is uniquely the set of unate cascade realizable functions. We also show that the APL for benchmark functions is typically much less than for random functions.
7. Representations of Logic Functions using QRMDDs
This part considers quasi-reduced Multi-valued decision diagrams with k bits (QRMDD(k)s) to represent two-valued logic function. It shows relations between the numbers of nodes in nodes in QRMDD(k)s and values of k for benchmark functions; an upper bound on the number of nodes in the QRMDD(k); difference between the upper bound and the number of nodes in the QRMDD(k)s for random function; and the amount of total memory, evaluation time, and area-time complexity for QRMDD(k)s. Experimental results using standard benchmark functions show that the area-time complexity takes its minimum when k is between 3 and 6.
8. Bi-Partition of Shared Binary Decision Diagrams
A shared binary decision diagram (SBDD) represents a multiple-output function, where nodes are shared among outputs. A partitioned SBDD usually consists of two or more SBDDs that often share nodes. The separate SBDDs are optimized independently, often resulting in a reduction in the number of nodes over a single SBDD. We show a method for partitioning a single SBDD into two parts that reduces the node the node count. Among the benchmark functions tested, a node reduction of up to 16% is realized.
9. Representation of Incompletely Specified Switching Functions Using Pseudo-Kronecker Decision Diagrams
Pseudo-Kronecher decision diagram (PKDD) is a generalization of binary decision diagram (BDD). A PKDD requires not more nodes than a BDD to represent the same function. In this part, we consider a method to represent incompletely specified functions by using PKDDs. We developed a heuristic method to obtain PKDDs. Many PKDDs for MCNC benchmark functions with don't cares are simplified. Experimental results show that the number of nodes of PKDD can be reduced by 14% by considering don't cares.
10. Compact BDD Representations for Multiple-Output Functions and Their Application
This part shows a new method to represent a multiple output function: an encoded characteristic function for nonzero outputs (ECFN). The ECFN uses (n + u) binary variables to represent an n-input m-output function, where u = [log_2m]. The binary decision diagrams (BDDs) for ECFNs are never greater than corresponding SBDDs. The size of a BDD depends on the encoding of the outputs as well as the ordering of the variables. We conjecture that there exists an n-input 2^n- output function, where the optimal encoding produces BDDs with 2n + 2 nodes, while the worst encoding produces BDDs with 2^<n+1> nodes. We formulate an encoding problem and show a heuristic method. Experimental results using standard benchmark functions show that the sizes of BDDs can be reduced significantly by considering encodings.
11. Fault Diagnosis for RAMs using Walsh Spectrum
In this part, we show a method to locate a single stuck-at fault of a random access memory (RAM). From the fail-bitmaps of the RAM, we obtain their Walsh spectrum. For single stuck-at fault, we show that the fault can be identified and located by using only the 0-th and 1-st coefficients of the spectrum. We also show a circuit to compute these coefficients. The computation time is much shorter than one that uses logic minimization method. Less
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