| Budget Amount *help |
¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 2002: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 2001: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 2000: ¥2,000,000 (Direct Cost: ¥2,000,000)
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| Research Abstract |
1. This research proposed a high-performance VLSI architecture for separable denominator 2-D state space digital filters based on reduced-dimensional decomposition. To obtainhigh-speed implementation, we aplied the highly parallel architecture based on the block algorithm. For the purpose of higher speed, small overhead is kept by using the distributed arithmetic of which processing time depends only on word length. Further, we can substantially decrease power dissipation by taking advantage of not the conventional distributed arithmetic using ROM's, but the method using the optimum function circuits which we have previously proposed. As a result of VLSI evaluation, we showed that this proposed architecture was very efficient for super high definition image.
2. Firstly, we proposed and analyzed the LMS adaptive filter using distributed arithmetic (DA-ADF), which used no multipliers (that is multiplier-less). Our proposed DA-ADF is a high-performance adaptive filter which has performances of high speed and small output latency, good convergence speed, small-scale hardware and lower power dissipation for higher order, simultaneously.
Secondly, for the purpose of further higher speed, we proposed block LMS algorithm using distributed arithmetic (BDA) and multi-memory block structured BDA (MBDA). To enable the pipelined processing, we applied an new update method to these algorithms. We called the method "priority update". Moreover, we proposed an efficient VLSI architecture of MBDA-ADF, and evaluated the sampling rate and output latency. As a result, our MBDA-ADF can achieve very high sampling rate and smal output latency.
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