| Budget Amount *help |
¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 2001: ¥1,200,000 (Direct Cost: ¥1,200,000)
Fiscal Year 2000: ¥2,200,000 (Direct Cost: ¥2,200,000)
|
|---|
| Research Abstract |
(1) For Reed-Muller codes and BCH codes, implementation of ACS (Add-Select-Compare) circuits based on its trellis structure has been studied. As a result, good trade-off is obtained for the circuit size and decoding delay. Dividing the entire decoding circuit into several 1C chips are also studied. As an example, a recursive maximum likelihood decoder of an (64, 40) subcode of (64, 42) Reed-Muller code can be implemented with the same decoding delay and the half of the circuit complexity.
(2) A divide and conquar algorithm has been devised to compute the weight distribution of the coset leadears. Although time complexity may be larger than known methods, the proposed method reduces the space complexity considerably. For the (64, 24), (64, 30), (128, 92), and (128, 99) extended primitive BCH codes, the (64, 22) and (128, 99) Reed-Muller codes and several other codes, we have computed the weight distribution of the coset leadears. For (64, 22) Reed-Muller codes, the space complexity becomes 1/40,000 of that of the conventional method. Also, it is shown for Reed-Muller codes that the natural symbol ordering and dividing the problem into half achieves the smallest space complexity.
(3) For Reed-Muller codes, the error performance of hard-decision and soft-decision majority logic decoding has been studied detailedly. As a result, the most decoding results in error are relatively far from the received word. Using this, a two step decoding method combined with decoding method with good error performance is proposed. This method reduces the decoding complexity.
|
