| Project/Area Number |
12838002
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
複合化集積システム
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
KURINO Hiroyuki Graduate School of Engineering, Tohoku University, Assistant Professor, 大学院・工学研究科, 助教授 (70282093)
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| Co-Investigator(Kenkyū-buntansha) |
洪 連基 東北大学, ベンチャー ビジネス ラボラトリー, 非常勤研究員
KOYANAGI Mitsumasa Graduate School of Engineering, Tohoku University, Professor, 大学院・工学研究科, 教授 (60205531)
HONG Young-gi Venture Business Laboratory, Tohoku Univ., Post Dr.
朴 起台 東北大学, 大学院・工学研究科, 助手 (50312608)
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| Project Period (FY) |
2000 – 2001
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| Project Status |
Completed (Fiscal Year 2001)
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| Budget Amount *help |
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 2001: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2000: ¥2,900,000 (Direct Cost: ¥2,900,000)
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| Keywords | Three Dimensional Integration Technology / Packaging / LSI / FPGA / Reconfigurable Logic / Image Processing / Parallel Processing / Semiconductor / 集積回路 / 半導体 / Vision Chip / Neuromorphic System / Biologically Inspired System |
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| Research Abstract |
In this work, we studied, the Three Dimensional Integrated Field Programmable Gate Array (3D FPGA) with Genetic Concept. Three Dimensional Integration Technology is a promising candidate to break through the limitation of present semiconductor technology ; wiring delay, power consumption, complex process of multiple wiring and so on. If three dimensional technology is applied to FPGA, the multi context 3D FPGA which can dynamically change the circuit configuration and functions, will be easily realized because a large volume of memory and FPGA logic circuits can be integrated into one chip with short wiring length. To realize such a 3D FPGA, we developed three dimensional integration technology and FPGA circuit technology in this work.
We developed five elemental process technologies to fabricate 3D FPGA ; Buried interconnection formation technology, Micro bump formation technology, Wafer thinning technology, Wafer alignment technology and Wafer bonding technology. Using these technologies, we fabricated 3D test chip which consisted of 3 device layers. It showed excellent electric characteristics of the 3D inverter chain and so on.
We also evaluated 3D FPGA circuits by the simulation and designed the FPGA circuits. As a result of evaluation, the multi context FPGA can be easily realized by three dimensional integration technology.
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