|Budget Amount *help
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2001: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 2000: ¥1,900,000 (Direct Cost: ¥1,900,000)
Genetic algorithms (GAs) are known to be robust and effective search algorithms for large-scale, complex optimization problems. In this research, we propose a new RISC processor, whose instruction set is tailored to the efficient execution of GAs. The proposed RISC Processor is designed based on the DLX instruction set, and we add several special instructions, which are effective to high-speed execution of GAs. Newly added instructions can be classified into three groups. The first group consists of bit-oriented instructions, because GA operators such as crossover often require bit-oriented operations. The second group consists of instructions concerning with random numbers. Since a GA frequently uses random numbers, the computation time for generating a pseudo-random number has a heavy effect on the performance of GA execution. The proposed processor has a pseudo-random number generation circuit, and in each clock cycle, a pseudo-random number is generated. The processor has several instructions using random numbers, which are very effective to shorten the computation time of selection, crossover, and mutation. Finally, the third group of instructions added to the proposed processor consists of SIMD instructions, which are mainly used to implement a crossover operation.
Since a GA is implemented as software on the proposed processor, any kind of GA can be realized. Simulation experiments show that, using the instruction set of the proposed processor, more than 90% reduction of the number of clocks to execute GA operators such as 2-point crossover can be achieved. The processor has been designed with the Verilog Hardware Description Language, and implemented as a VLSI chip with a 0.35μm standard cell technology. The fabricated LSI chip was tested to show all the instructions of the proposed processor were executed correctly.