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Development of "Hardware Morphing" Technology for Dynamic Optimization of Hardware Configuration

Research Project

Project/Area Number 13308015
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionKyushu University

Principal Investigator

MURAKAMI Kazuaki  Kyushu University, Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (10200263)

Co-Investigator(Kenkyū-buntansha) MATSUNAGA Yusuke  Kyushu University, Faculty of ISEE, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
FUKUDA Akira  Kyushu University, Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80165282)
YASUURA Hiroto  Kyushu University, Faculty of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
INOUE Sozo  Kyushu University, Faculty of ISEE, Research Associate, 大学院・システム情報科学研究院, 助手 (90346825)
IWAIHARA Mizuho  Kyoto Univ., Grad.School of Informatics, Associate Professor, 大学院・情報学研究科, 助教授 (40253538)
冨山 宏之  (財)九州システム情報技術研究所, 第1研究室, 研究員
富山 宏之  (財)九州システム情報技術研究所, 第1研究室, 研究員
澤田 直  九州大学, 大学院・システム情報科学研究院, 助手 (70235464)
Project Period (FY) 2001 – 2003
Project Status Completed (Fiscal Year 2003)
Budget Amount *help
¥51,740,000 (Direct Cost: ¥39,800,000、Indirect Cost: ¥11,940,000)
Fiscal Year 2003: ¥6,110,000 (Direct Cost: ¥4,700,000、Indirect Cost: ¥1,410,000)
Fiscal Year 2002: ¥19,630,000 (Direct Cost: ¥15,100,000、Indirect Cost: ¥4,530,000)
Fiscal Year 2001: ¥26,000,000 (Direct Cost: ¥20,000,000、Indirect Cost: ¥6,000,000)
Keywordssystem LSI / dynamic optimization / computer architecture / profiling / low power design / optimizing compiler / adaptive control / circuit design
Research Abstract

The objective of this research project is to develop techniques(called "Syste Morph : System Morphing") of dynamic reconfiguration and optimization of hardware for system-LSI's and software for them, as (a)an approach for optimization of designing system-LSI's and (b)a solution for "design crisis". The project has performed the following research results.
(1)Development and evaluation of online-pro filing techniques : The project has developed some techniques of online profiling which find a hot spot(for example, programming codes, data, or paths operated frequently in a program) by observing the behavior of a program. Then, the project has implemented the online profile to the, dynamically-reconfigurable processor, DAP/DNA, by IPFlex, and evaluated its accuracy and overheads.
(2)Development and evaluation of dynamic-software-pipelining techniques : The project has developed some techniques of dynamic software pipelining for loops in the hot path found in (1). Then, the project has implemented the techniques for a hyper-scalar processor which has a VLIW as its coprocessor, and evaluated its improvement and overheads.
(3)Development and evaluation of online-construction techniques for configuration data of hardware : The project has developed some techniques to construct the configuration data of a DNA dynamically and in a parallel with the operation of the program, to con figure dynamically the hot path in (1) to the DNA as a logical circuit. Then, the project has implemented the techniques and valuated its performance

Report

(4 results)
  • 2003 Annual Research Report   Final Research Report Summary
  • 2002 Annual Research Report
  • 2001 Annual Research Report
  • Research Products

    (44 results)

All Other

All Publications (44 results)

  • [Publications] H.Akaboshi et al.: "Case Study : Mapping Telecommunication Functions to Fine Grain Multiprocessor System (FPSA)"Proc.of International Symposium on Low-Power and High-Speed Chips (COOL Chips IV). 345 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] T.Okuma et al.: "A System-level Energy Minimization Approach Using Datapath Width Optimization"IEEE Design & Test of Computers. 18・2. 32-41 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Y.Cao et al.: "Software Energy Reduction Techniques for Variable Voltage Processors"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'01). 231-236 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue et al.: "Dynamic Tag-Check Omission : A Low-Power Instruction Cache Architecture Exploiting Execution Footprints"Proc.of Workshop on Power Aware Computer Systems (PACS'02). 15-21 (2001)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue et al.: "Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors"IEICE Transactions on Electronics. E85-C(2). 279-287 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue et al.: "Trends in High-Performance, Low-Power Cache Memory Architectures"IEICE Transactions on Electronics. E85-C(2). 304-314 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue et al.: "A History-Based I-Cashe for Low-Energy Multimedia Applications"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'02). 148-153 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue et al.: "A Low Energy Set-Associative I-Cashe with Extended BTB"Proc.of International Conference on Computer Design (ICCD'02). 187-192 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue et al.: "Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality"IEICE Trans.FUNDAMENTALS. 86-A(4). 799-805 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] V.Goulart et al.: "Dynamic Effective Precision Matching Computation"Proc.The 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2003). 230-237 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] T.Hayashida et al.: "Evaluating Online Hot Instruction Sequence Profilers for Dynamically Reconfigurable Functional Units"IEICE Trans.Information and Systems. E86-D(5). 901-909 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Metsugi et al.: "Relaxing Constraints due to Data and Control Dependences"IEICE Trans.Information and Systems. E86-D(5). 920-928 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] T.Hayashida et al.: "Evaluating Online Hot Instruction Sequence Profiler Using Jumble-Counting Method"Proc.International Symposium on Information Science and Electrical Engineering 2003 (ISEE2003). 55-58 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] H.Akaboshi et al.: "Case Study : Mapping Telecommunication Functions to Fine Grain Multiprocessor System(FPSA)"Proc.of International Symposium on Low-Power and High-Speed Chips(COOL Chips IV). 345 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] T.Okuma et al.: "Software Energy Reduction Techniques for Variable Voltage Processors"IEEE Design & Test of Computers. 18(2). 32-41 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Y.Cap et al.: "A System-level Energy Minimization Approach Using Datapath Width Optimization"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'01). 231-236 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue, et al.: "Dynamic Tag-Check Omission : A Low-Power Instruction Cache Architecture Exploiting Execution Footprints"Proc.of Workshop on Power Aware Computer Systems(PACS'02). 15-22 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue, et al.: "Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors"IEICE Transactions on Electronics. 279-287 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue, et al.: "Trends in High-Performance, Low-Power Cache Memory Architectures"IEICE Transactions on Electronics. 304-314 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue, et al.: "A History-Based I-Cashe for Low-Energy Multimedia Applications"Proc.of International Symposium on Low Power Electronics and Design (ISLPED'02). 148-153 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue, et al.: "A Low Energy Set-Associative I-Cashe with Extended BTB"Proc.of International Conference on Computer Design(ICCD'02). 187-192 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Inoue, et al.: "Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality"IEICE Trans.FUNDAMENTALS. 86-A(4). 799-805 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] V.Goulart, et al.: "Dynamic Effective Precision Matching Computation"Proc.The 11th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI 2003). 230-237 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] T.Hayashida, et al.: "Evaluating Online Hot Instruction Sequence Profilers for Dynamically Reconfigurable Functional Units"IEICE Trans.Information and Systems. E86-D(5). 901-909 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] K.Metsugi, et al.: "Relaxing Constraints due to Data and Control Dependences"IEICE Trans.Information and Systems. E86-D(5). 920-928 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] T.Hayashida, et al.: "Evaluating Online Hot Instruction Sequence Profiler Using Jumble-Counting Method"Proc.International Symposium on Information Science and Electrical Engineering 2003(ISEE2003). 55-58 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Koji Inoue et al.: "Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality"IEICE TRANS.FUNDAMENTALS. 86-A・4. 799-805 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Victor Goulart et al.: "Dynamic Effective Precision Matching Computation"Proc.The 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2003). 230-237 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Takanori Hayashida et al.: "Evaluating Online Hot Instruction Sequence Profilers for Dynamically Reconfigurable Functional Units"IEICE Trans. Information and Systems. E86-D・5. 901-909 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Katsuhiko Metsugi et al.: "Relaxing Constraints due to Data and Control Dependences"IEICE.Trans Information and Systems. E86-D・5. 920-928 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] ヴィクトル マウロ グラール フェヘイラほか: "Dynamic Effective Precision Matching Computationによる低消費電力化"電子情報通信学会論文誌C. J86・8. 817-825 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Takanori Hayashida et al.: "Evaluating Online Hot Instruction Sequence Profiler Using Jumble-Counting Method"Proc.International Symposium on Information Science and Electrical Engineering 2003(ISEE2003). 55-58 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] K.Inoue et al.: "A History-Based I-Cashe for Low-Energy Multimedia Applications"Proc. of International Symposium on Low Power Electronics and Design(ISLPED'02). 148-153 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 田上裕之, ほか: "動的ソフトウェアパイプライニング技術の提案と性能評価"情報処理学会研究報告. ARC149-15. 85-90 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 松尾 烈, ほか: "Dependable Pipelining : マルチGHz時代のマイクロアーキテクチャ"電子情報通信学会技術研究報告. DC2002-20. 25-30 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 目次勝彦, ほか: "スレッドレベル投機的並列処理アーキテクチャにおけるデータ依存制約緩和手法の効果"情報処理学会論文誌. 43・SIG6. 24-33 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] K.Inoue et al.: "A Low Energy Set-Associative I-Cashe with Extended BTB"Proc. of International Conference on Computer Design(ICCD'02). 187-192 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] L.Gauthier et al.: "A Front-End for Better Behavioral Synthesis"電子情報通信学会技術研究報告. CPSY2002-63. 31-36 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] H.Akaboshi et al.: "Case Study : Mapping Telecommunication Functions to Fine Grain Multiprocessor System (FPSA)"Proc. of International Symposium on Low-Power and High-Speed Chips (COOL Chips IV). 345 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] T.Okuma et al.: "Software Energy Reduction Techniques for Variable Voltage Processor"IEEE Design & Test of Computers. 18・2. 32-41 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Y.Cao et al.: "A System-level Energy Minimization Approach Using Data path Width Optimization"Proc. of International Symposium on Low Power Electronics and Design (ISLPED'01). 231-236 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] K.Inoue et al.: "Dynamic Tag-Check Omission : A Low-Power Instruction Cache Architecture Exploiting Execution Footprints"Proc. of Workshop on Power Aware Computer Systems (PACS'02). 15-22 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] K.Inoue et al.: "Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors"IEICE Transactions on Electronics. E85-C・2. 279-287 (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] K.Inoue et al.: "Trends in High-Performance, Low-Power Cache Memory Architectures"IEICE Transactions on Electronics. E85-C・2. 304-314 (2002)

    • Related Report
      2001 Annual Research Report

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Published: 2001-04-01   Modified: 2016-04-21  

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