| Project/Area Number |
13450014
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Applied materials science/Crystal engineering
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| Research Institution | Himeji Institute of Technology |
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Principal Investigator |
YOSHIDA Haruhiko Himeji Institute of Technology, Graduate School of Engineering , Associate Professor, 大学院・工学研究科, 助教授 (90264837)
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| Co-Investigator(Kenkyū-buntansha) |
KISHINO Seigo Himeji Institute of Technology, Graduate School of Engineering, Professor, 工学研究科, 教授 (50201455)
内橋 貴之 姫路工業大学, 工学部, 助手 (30326300)
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| Project Period (FY) |
2001 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥12,000,000 (Direct Cost: ¥12,000,000)
Fiscal Year 2002: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2001: ¥10,600,000 (Direct Cost: ¥10,600,000)
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| Keywords | ContactLess Characterization / Localized States / Lifetime / Capacitance-Voltage Method / Capacitance Transient / Capacitance-frequency Method / Water Mapping / SOI Wafer / 容量-電圧特性 / 容量-周波数特性 / 局在凖位 / 走査型容量顕微鏡 / SOI |
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| Research Abstract |
In this research, scanning capacitance transient spectroscopy was developed for obtaining a spatial distribution of localized states and carrier lifetime. In this method, a wafer mapping of electrical characteristics can be obtained by scanning a contactless electrode on a wafer. In order to demonstrate the validity of the developed method, a wafer map of generation lifetime of minority carriers were measured. Zerbst method was applied to the contactless characterization for the measurement of a spatial distribution of carrier lifetime. By comparison with conventional Zerbst method, it was found that the contactless Zerbst method enabled us to obtain carrier lifetime as well as the conventional method. Furthermore, it was demonstrated that a wafer mapping of carrier lifetime could be characterized by using scanning capacitance transient spectroscopy.
Moreover, a capacitance-frequency (C-f) method was applied to the characterization of heavy metal contamination. In this study, the characterization of generation lifetime, interface traps, and bulk traps based on the C-f measurement was carried out. The validity of this method was assured with the use of Cu-doped and Au-doped samples.
Also, a capacitance-voltage (C-V) method was proposed to separately characterize charges in respective oxide films and interface traps at the respective interfaces of SOI (Silicon-on-Insulator) wafer. In the proposed C-V method, a capacitance of SOI-MOS capacitor is measured between a front-gate electrode and SOI body contact interconnected to a back-gate electrode. The respective oxide charges and interface traps are estimated from dependence of SOI-MOS capacitance on a front-gate or a back-gate voltage.
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