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Design Methodology for Advanced VLSI Systems with Heterogeneous Timing

Research Project

Project/Area Number 13480076
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionThe University of Tokyo

Principal Investigator

NANYA Takashi  Research Center for Advanced Science and Technology, Professor, 先端科学技術研究センター, 教授 (80143684)

Co-Investigator(Kenkyū-buntansha) IMAI Masashi  Research Center for Advanced Science and Technology, Research Associate, 先端科学技術研究センター, 助手 (70323665)
NAKAMURA Hiroshi  Research Center for Advanced Science and Technology, Associate Professor, 先端科学技術研究センター, 助教授 (20212102)
Project Period (FY) 2001 – 2002
Project Status Completed (Fiscal Year 2002)
Budget Amount *help
¥17,200,000 (Direct Cost: ¥17,200,000)
Fiscal Year 2002: ¥6,600,000 (Direct Cost: ¥6,600,000)
Fiscal Year 2001: ¥10,600,000 (Direct Cost: ¥10,600,000)
KeywordsLocally timed VLSI / CAD / AINOS / SDl model / Verilog RTL / Asynchronous Circuit / DI Interface / 2線2相式データ転送 / 暗号化回路 / 同期・非同期融合型VLSIシステム / CAD / 事象駆動原理 / 非同期式ライブラリ / STG / ダブルバッファDDL / メモリアーキテクチャ
Research Abstract

In this work, we proposed a design method for locally timed VLSI systems in terms of a scalable delay insensitive (SDI) model. In the SDI model, although unbounded gate and wire delays are assumed, the relative delay information among gates and wires is obtained. Therefore, by using such an information, area and performance optimum VLSI systems can be designed. In addition, we developed the CAD system named AINOS and the design library to facilitate out proposed design method. In AINOS, a Verilog RTL description is accepted as the input and corresponding asynchronous system is synthesized. During the synthesis, pairs of handshake signals to realize asynchronous communication are inserted, circuits to control handshake signals are generated, and the timing verification for handshake signals is realized. Since AINOS accepts the same description used in commonly used synchronous system designs, one can design locally timed systems easily if he is familiar with the Verilog description.
Together with AINOS development, we proposed several methods for the logic synthesis of locally timed VLSI systems. At first, to solve the wire delay problem, we proposed a design method so that the interface of circuits is insensitive to wire delays. As a result, the circuit can correctly operate under arbitrary wire delay for input wires. Next, to optimize asynchronous control circuits, we extended a boolean optimization method named transduction method to apply it for asynchronous control circuits. At last, we proposed a design method of control circuits to control data-path circuits with variable delay arithmetic units.

Report

(3 results)
  • 2002 Annual Research Report   Final Research Report Summary
  • 2001 Annual Research Report
  • Research Products

    (41 results)

All Other

All Publications (41 results)

  • [Publications] Hiroshi Saito: "Designs of Asynchronous Controllers with Delay Insensitive Interface"IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences. E85-A, No.12. 2577-2585 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Nattha Sretasereekul: "Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits"IEICE Trans. on Fundamentals. E86-A, No.4. 900-907 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] 今井 雅: "SDIモデルに基づく局所同期型非同期式VLSI設計方式"情報処理学会論文誌. Vol.44, No.5. (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Metehan Ozcan: "Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits"Trans. of IPSJ. Vol.44, No.5. (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito: "Designs of Asynchronous Controllers with Delay Insensitive Interface"Proc. Asia South Pacific Design Automation Conference. Jan.. 93-98 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Metehan Ozcan: "Generation and Verification of Timing Constrains for Fine-Grain Pipelined Asynchrounous Data-Path Circuits"Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. Apr.. 109-114 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Nattha Sretasereekul: "Flexible Partitioning of CDFGs for Compact Asynchronous Controllers"Proc. International Technical Conference on Circuits/Systems, Computers and Communications. Jul.. 1724-1727 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito: "An Equivalence Checking Methodology for Hardware Oriented C-based Specifications"Proc. IEEE International High Level Design Validation and Test Workshop. Oct.. 139-144 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Euiseok Kim: "Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units"Proc. Asia South Pacific Design Automation Conference. Jan.. 816-819 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito: "Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method"Proc. Asia South Pacific Design Automation Conference. Jan.. 197-202 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Euiseok Kim: "Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units"Proc. Design, Automationan and Test in Europe. Mar.. (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito: "Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions"Proc. IEEE International Symposium on Asynchronous Systems and Circuits. May. (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito et al.: "Designs of Asynchronous Controllers with Delay Insensitive Interface"IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences. E85-A, No.12. 2577-2585 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Nattha Sretasereekul et al.: "Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits"IEICE Trans. on Fundamentals. E86-A No.4. 900-907 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Masashi Imai et al.: "An SDI Model based Design Methodology for Locally-Timed Asynchronous Circuits"Trans. of lPSJ. 44, No.5. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Metehan Ozcan et al.: "Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits"Trans. of IPSJ. 44, No.5. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito et al.: "Designs of Asynchronous Controllers with Delay Insensitive Interface"Proc. Asia South Pacific Design Automation Conference. 93-98 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Metehan Ozcan et al.: "Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits"Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. 109-114 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Nattha Sretasereekul et al.: "Flexible Partitioning of CDFGs for Compact Asynchronous Controllers"Proc. International Technical Conference on Circuits/Systems, Computers and Communications. 1724-1727 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito et al.: "An Equivalence Checking Methodology for Hardware Oriented C-based Specifications"Proc. IEEE International High Level Design Validation and Test Workshop. 139-144 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Euiseok Kim et al.: "Performance Optimization of Synchronous Control Units for Datapaths with Variable Delay Arithmetic Units"Proc. Asia South Pacific Design Automation Conference. 816-819 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito et al.: "Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method"Proc. Asia South Pacific Design Automation Conference. 197-202 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Euiseok Kim et al.: "Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units"Proc. Design, Automation and Test in Europe. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Hiroshi Saito et al.: "Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions"Proc. IEEE International Symposium on Asynchronous Systems and Circuits. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2002 Final Research Report Summary
  • [Publications] Metehan Ozcan: "Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits"Proc. of Async 2002. 109-114 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 齋藤 寛: "非同期回路におけるデータパス遅延情報を用いた制御信号共有化手法"電子情報通信学会技術報告 CPSY2002-67. 97-101 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 月坂 真之: "ダイナミック回路のプリチャージ期間を隠蔽する手法を用いた高速データパスの実現"電子情報通信学会技術報告 VLD. 276-281 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] Hiroshi Saito: "Logic Optimization for Asynchronous Speed Independent Controllers Using Transduction Method"Proc. of ASP-DAC 2003. 197-202 (2003)

    • Related Report
      2002 Annual Research Report
  • [Publications] 今井 雅: "SDIモデルに基づく局所同期型非同期式VLSI設計方式"情報処理学会論文誌. (in press). (2003)

    • Related Report
      2002 Annual Research Report
  • [Publications] Metehan Ozcan: "Verification and Violation Correction of Timing Constraints for Gate-Level Asynchronous Circuits"情報処理学会論文誌. (in press). (2003)

    • Related Report
      2002 Annual Research Report
  • [Publications] 今井 雅: "遅延情報を利用した非同期式VLSI設計の一手法の提案"電子情報通信学会技術研究報告. Nov.. 51-56 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 宮沢 義幸: "非同期式VLSI設計用CADシステムの提案"電子情報通信学会VLSI設計技術研究会. May. 9-14 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Hiroshi Saito: "Design of Asynchronous Controllers with Delay Insensitive Interface"Proc.of ASP-DAC/VLSI Design. Jan.. 93-98 (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] Metehan Ozcan: "Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchrounous Data-Path Circuits"Proc. of ASYNC2002. Apr.. (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] N.Hosaka: "Comparison of Methods for Probe Design"Genome Informatics 12. Des.. 449-450 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 小沢 基一: "Cascade ALUアーキテクチャにおける性能スケーラビリティの評価"「知的瞬時処理複合化集積システム」公開シンポジウム. Mar.. (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] 近藤 正章: "SCIMAにおける性能最適化手法の検討"情報処理学会研究会論文誌HPS. 42. 37-48 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 大根田 拓: "SCIMAにおけるメモリアクセス制御機構の検討"情報処理学会計算機アーキテクチャ研究会. ARC4-29. 165-170 (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] M.Fujita: "The Standard SpecC Language"Proc.of ISSS2001. Oct.. 37-48 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 藤田 元信: "ソフトウェア制御オンチップメモリのための最適化コンパイラの構想"情報処理学会計算機アーキテクチャ研究会. ARC-146. 31-36 (2002)

    • Related Report
      2001 Annual Research Report
  • [Publications] 大根田 拓: "SCIMAにおけるメモリアクセス機構の設計と評価"情報処理学会計算機アーキテクチャ研究会(HOKKE2002). ARC-147. 79-84 (2002)

    • Related Report
      2001 Annual Research Report

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Published: 2001-04-01   Modified: 2016-04-21  

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