| Project/Area Number |
13555094
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | KYOTO UNIVERSITY |
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Principal Investigator |
KIMOTO Tsunenobu Kyoto University, Department of Electronic Science and Engineering, Associate Professor, 工学研究科, 助教授 (80225078)
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| Co-Investigator(Kenkyū-buntansha) |
SUDA Jun Kyoto University, Department of Electronic Science and Engineering, Lecturer, 工学研究科, 講師 (00293887)
MATSUNAMI Hiroyuki Kyoto University, Department of Electronic Science and Engineering, Professor, 工学研究科, 教授 (50026035)
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| Project Period (FY) |
2001 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥10,300,000 (Direct Cost: ¥10,300,000)
Fiscal Year 2002: ¥4,300,000 (Direct Cost: ¥4,300,000)
Fiscal Year 2001: ¥6,000,000 (Direct Cost: ¥6,000,000)
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| Keywords | Silicon Carbide / Power Device / MOSFET / Oxide / Semiconductor Interface / Channel Mobility |
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| Research Abstract |
Control of MOS interface, device processing, and fabrication of high-voltage MOSFETs have been investigated by using a wide bandgap semiconductor silicon carbide (SiC), which shows high breakdown field and other excellent physical properties. In control of MOS interface, thermal oxidation at high temperature resulted in the improvement of the MOS quality, and high channel mobilities of 78 cm^2/Vs and 22 cm^2/Vs were obtained for 6H-SiC(OOOl) and 4H-SiC(OOOl) MOSFETs, respectively. 4H-SiC(ll20) and (0338) MOSFETs exhibited a high channel mobility of 30-40 cm^2/Vs. In device processing, thick SiO_2 films deposited by plasma CVD could successfully used as an implantation mask. Short-channel MOSFETs with a channel length of 1 μm could be processed. The electrical activation of implanted dopants was significantly improved by increasing annealing temperature after implantation. The structure of lateral SiC MOSFETs with RESURF (Reduced Surface Field) structure was designed by using a 2D device simulation. The RESURF dose, depth, and the drift layer structure were optimized. SiC lateral RESURF MOSFETs were fabricated on 4H-SiC and 6H-SiC which were grown in our group. The MOSFET showed a very high breakdown voltage of 1 kV and a low on-resistance of 0.1 Ωcm^2. This characteristics outperforms the "Si limit" which is theoretically determined from the material properties, demonstrating the much potential of SiC power devices.
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