| Project/Area Number |
13558026
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku University |
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Principal Investigator |
HANYU Takahiro Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (40192702)
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| Co-Investigator(Kenkyū-buntansha) |
KAMEYAMA Michitaka Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (70124568)
MOCHIZUKI Akira Tohoku University, Research Institute of Electrical Communication, Research Associate, 電気通信研究所, 助手 (40359542)
KIMURA Hiromitsu Tohoku University, Graduate School of Information Sciences, Research Associate, 大学院・情報科学研究科, 助手 (00361155)
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| Project Period (FY) |
2001 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥13,600,000 (Direct Cost: ¥13,600,000)
Fiscal Year 2004: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 2003: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2002: ¥2,000,000 (Direct Cost: ¥2,000,000)
Fiscal Year 2001: ¥8,200,000 (Direct Cost: ¥8,200,000)
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| Keywords | multiple-valued logic-in-memory / TMR device / ferroelectric capacitor / fully parallel processing / device modeling / resistor-circuit network / storage / operation merging / data-transfer bottleneck / 強誘電体デバイス / 全加算器 / デバイスモデル / 非破壊読出し / 相補的動作 / 強誘電体CAM / 不揮発性ロジック / FPGA / ゲートレベルパイプライン / フローティングゲートMOSトランジスタ / 多値集積回路 / パイプライン乗算器 / ゲートレベルパイプライン処理 / マイクロ順序動作 / 多値基本演算子 |
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| Research Abstract |
Dramatic advances in technology scaling give us the capability to realize a giga-scaled system-on-a-chip, while rapid increases in the wiring complexity and the global wiring delay has led to serious data-transfer bottleneck between separated logic modules and memories in current deep-submicron VLSI. Logic-in-memory structures, where storage functions are distributed over a logic-circuit plane, provide a key architecture for ensuring highly effective use of internal memory bandwidth. However, usual logic-in-memory VLSI becomes generally complicated, because of the hardware overhead involved in distributing storage elements. In this research, I have presented ferroelectric-based (FE-based) functional logic gates for highly parallel VLSI systems. In FE-based logic gates, since both non-volatile storage and switching functions are performed simultaneously in FE capacitors, chip size and a leakage current can be reduced. As a typical application of this circuit technology, a 54x54-bit pipe
… More
lined multiplier is implemented and its superior performance is demonstrated. Furthermore, I have also developed the improved ferroelectric-based logic circuit, called a "Complementary-Ferroelectric-Capacitor (CFC)" logic for low-power logic-in-memory VLSI. Using two FE capacitors where a pair of complementary data representations is stored, the voltage swing generated by capacitive coupling effect becomes large enough to perform the switching operation at the low supply voltage. Degradation of the non-volatile charge caused by the switching operation becomes small because the bias voltage appeared across the FE capacitor is always lower than its coercive voltage. As a typical example, a 32-bit content-addressable memory (CAM) is also implemented and its superior performance is demonstrated. Finally, a tunneling magnetoresistive (TMR)-based logic-in-memory circuit has been also proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability any logic functions between external inputs and stored inputs can be performed by using the TMR based resistor/transistor network The combination of a dynamic current-mode logic circuit and a TMR-based network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of a full adder is discussed, and its advantages are demonstrated. Less
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