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A Study on How Implementing Microprocessors Exploiting Instruction Level Parallelism

Research Project

Project/Area Number 13558030
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionKyushu Institute of Technology

Principal Investigator

SATO Toshinori  Kyushu Institute Of Technology, Associate Professor, 情報工学部, 助教授 (00322298)

Project Period (FY) 2001 – 2003
Project Status Completed (Fiscal Year 2003)
Budget Amount *help
¥6,900,000 (Direct Cost: ¥6,900,000)
Fiscal Year 2003: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2002: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 2001: ¥4,900,000 (Direct Cost: ¥4,900,000)
KeywordsILP / Processors / Reissue / Fault Tolerance / Speculation / Power / Critical Path / LSI / プロセッサ / エネルギー / 信頼性 / スーパースカラ / 半導体技術 / 命令レベル並列処理
Research Abstract

Power consumption is a major concern in embedded microprocessors design.Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power..Regarding the effect of sustaining throughput on power and performance, it is found that pipelined functional units are better in energy reduction as well as in performance than non-pipelined units even if the increase in hardware due to extra latches are considered. We also evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is currently not a good design choice for energy efficiency.

Report

(4 results)
  • 2003 Annual Research Report   Final Research Report Summary
  • 2002 Annual Research Report
  • 2001 Annual Research Report
  • Research Products

    (21 results)

All Other

All Publications (21 results)

  • [Publications] 佐藤寿倫, 有田五次郎: "可変レイテンシパイプライン技術と演算結果再利用技術の併用による演算レイテンシ削減"電子情報通信学会論文誌D-I. J85-D-1. 1103-1113 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Toshinori Sato, Kiichi Sugitani, Akihiko Hamano, Itsujiro Arita: "Evaluating Influence of Compiler Optimizations on Data Speculation"Journal of Information Science and Engineering. Vol.18. 1027-1036 (2002)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] 神代剛典, 佐藤寿倫: "低消費電力指向マルチスレッドプロセッサのための低コスト値予測機構の検討"情報処理学会論文誌コンピューティングシステム. 45. 43-53 (2004)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Toshinori Sato: "A Transparent Transient Faults Tolerance Mechanism for Superscalar Proc essors"IEICE Transactions on Information and Systems. E86-D. 2508-2516 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] 千代延昭宏, 佐藤寿倫, 有田五次郎: "低消費電力プロセッサアーキテクチャ向けクリティカルパス予測器の評価"電子情報通信学会論文誌C. J86-C. 826-835 (2003)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Toshinori Sato, Itsujiro Arita: "Combining Variable Latency Pipeline with Instruction Reuse for Execution Latency Reduction"IEICE Transactions on Information and Systems. vol.J85-D-I, no.12, December. (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Toshinori Sato, Kiichi Sugitani, Akihiko Hamano, Itsujiro Arita: "Evaluating Influence of Compiler Optimizations on Data Speculation"Journal of Information Science and Engineering. vol.18,no.6 November. (2002)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Takenori Koushiro, Toshinori Sato: "A Low-Cost Value Predictor for Energy-Efficient Speculative Multithreaded Processors"IPSJ Transactions on Advanced Computing Systems. vol.45, no.SIG1(ACS 4) January. (2004)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Toshinori Sato: "A Transparent Transient Faults Tolerance Mechanism for Superscalar Processors"IEICE Transactions on Information and Systems. vol.E86-D, no.12 December. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] Akihiro Chiyonobu, Toshinori Sato, Itsujiro Arita: "An Evaluation of Critical Path Predictors for Low Power Processor Architecture"IEICE Transactions on, Electronics. vol.J86-C, no.8 August. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2003 Final Research Report Summary
  • [Publications] 神代剛典, 佐藤寿倫: "低消費電力指向マルチスレッドプロセッサのための低コスト値予測機構の検討"情報処理学会論文誌コンピューティングシステム. 45(SIG1). 43-53 (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] Toshinori Sato: "A Transparent Transient Faults tolerance Mechanism for Superscalar Processors"IEICE Transactions on Information and Systems. E86-D(12). 2508-2516 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 千代延昭宏, 佐藤寿倫, 有田五次郎: "低消費電力プロセッサアーキテクチャ向けクリティカルパス予測器の評価"電子情報通信学会論文誌C. J86-C(8). 826-835 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 佐藤寿倫, 有田五次郎: "可変レイテンシパイプライン技術と演算結果再利用技術の併用による演算レイテンシ削減"電子情報通信学会論文誌D-I. J85-D-I・12. 1103-1113 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] Toshinori Sato, Kiichi Sugitani, Akihiko Hamano, Itsujiro Arita: "Evaluating Influence of Compiler Optimizations on Data Speculation"Journal of Information Science and Engineering. Vol.18・No.6. 1027-1036 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 佐藤寿倫, 有田五次郎: "過渡故障に対するマイクロプロセッサ向けフォールトトレランス技術の提案"並列処理シンポジウム予稿集. 335-342 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Toshinori Sato, Itsujiro Arita: "Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse"Proc. 7^<th> International Euro-Par Conference. 428-438 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Toshinori Sato, Itsujiro Arita: "Transient Faults Tolerance Mechanism for Microprocessors"Proc. 2^<nd> International Conference on Dependable Systems and Networks. B8-B9 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] 佐藤寿倫, 有田五次郎: "マイクロプロセッサ向けフォールトトレランス技術におけるペナルティ削減"電子情報通信学会技術報告. FTS2001. 25-31 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Toshinori Sato, Itsujiro Arita: "Tolerating Transient Faults through an Instruction Reissue Mechanism"Proc. 14^<th> International Conference on Parallel and Distributed Computing Systems. 240-247 (2001)

    • Related Report
      2001 Annual Research Report
  • [Publications] Toshinori Sato, Toshiyuki Yamamoto, Itsujiro Arita: "The KIT COSMOS Processor : Some Ideas on Realizing Complexity-Effective Superscalar Processors"Proc. 2^<nd> International Conference on Software Engineering, Artificial Intelligence, Networking & Parallel/Distributed Computing. 549-556 (2001)

    • Related Report
      2001 Annual Research Report

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Published: 2001-04-01   Modified: 2016-04-21  

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