| Project/Area Number |
13650011
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Applied materials science/Crystal engineering
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| Research Institution | Shizuoka University |
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Principal Investigator |
ISHIKAWA Yasuhiko Shizuoka University, Research Institute of Electronics, Research Associate, 電子工学研究所, 助手 (60303541)
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| Co-Investigator(Kenkyū-buntansha) |
TABE Michiharu Shizuoka University, Research Institute of Electronics, Professor, 電子工学研究所, 教授 (80262799)
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| Project Period (FY) |
2001 – 2003
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| Project Status |
Completed (Fiscal Year 2003)
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| Budget Amount *help |
¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 2003: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 2002: ¥1,000,000 (Direct Cost: ¥1,000,000)
Fiscal Year 2001: ¥1,400,000 (Direct Cost: ¥1,400,000)
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| Keywords | SOI / thermal agglomeration / Si islands / line structure / patterning / waveguide / selective area formation / optical devices |
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| Research Abstract |
In this work, thermal agglomeration of line-patterned SOI (silicon-on-insulator) structures (SOI waveguides) was studied in order to form one-dimensional periodic structure for the application to optical devices such as channel dropping filters.
Selective area formation of Si islands was realized using the spatial modulation of initial SOT layer. Partial passivation with thermally grown SiO_2 was also found to be effective for the selective area islanding.
As for the islanding of SOI line structures, effect of line width, SOI thickness, in-plane crystalline direction of the line pattern and fabrication process (local oxidation of Si or wet etching) was studied. As a result, annealing the SOI line structure having submicron width and thickness of 〜3 nm by the local oxidation technique was found to be deformed into island arrays aligned along two edges of line pattern with the residual Si layer between the arrays. Reflecting the fact that the alignment occurs independent of the in-plane crystalline direction of line pattern, island alignment along the line edges is maintained at 90^O-bend and T-branch of the pattern. This island array can be applied to the multiple-tunnel-junction array, since the island size is as small as 50 nm and the residual Si layer connects the islands as the tunnel capacitors.
When the larger width/thickness of line pattern is prepared or when the wet etching process is used in the fabrication, the regular array is not formed. 7-nm-thick SOI layer is required for the fabrication of Si islands with the diameter of 〜100 nm, which is effective for photonic crystal applications, but in this case, the island is not aligned. Further study is necessary in this point.
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