| Budget Amount *help |
¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2002: ¥1,500,000 (Direct Cost: ¥1,500,000)
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| Research Abstract |
An indirect addressing digital signal processors (hereafter DSP) with auto-modification is assumed, a new code optimization technique is proposed, where memory allocation phase is intensively coupled with a computational ordering phase.
In general, software development for DSP is highly cost consuming, so that powerful programming tools such as high-level language compiler is strongly desired. High performance in generated program codes is usually achieved by effective use of arithmetic units and registers. In most of DSPs, however, memory addressing modes are simplified and efficient memory access becomes another key to achieve high code performance.
In this research project, a DSP with indirect addressing with auto-modification is assumed, and its compiler has such structure that computational order is rearranged in intermediate code of sub-instruction level according to the derived arithmetic register assignment and memory allocation. The compiler first counts usage of each variable in the data flow graph (hereafter DFG) of a given program, and selects program variables to be spilled. For the derived DFG, the number of overhead codes is evaluated by code generation followed by memory allocation. Then for the commutative arithmetic operations with memory access, the number of overhead codes is evaluated for all the alternative computational orders, and finally, the code with least overhead code is taken as the result.
The proposed code optimization technique is applied to the existing compiler for mPD77230, which has similar memory addressing. Codes generated by the compiler for several examples includes less overhead codes associated with memory access than those derived by conventional compilers, and hence shows the effectiveness of the proposed code optimization technique.
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