| Project/Area Number |
13680216
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Science education
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| Research Institution | Ariake National College of Technology |
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Principal Investigator |
NAKAMURA Shunzaburo Ariake National College of Technology, Department of Electronics and Information engineering, Professor, 電子情報工学科, 教授 (00227901)
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| Project Period (FY) |
2001 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥1,200,000 (Direct Cost: ¥1,200,000)
Fiscal Year 2002: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 2001: ¥700,000 (Direct Cost: ¥700,000)
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| Keywords | engineering education / semiconductor engineering / integrated circuit / CMOS / MOSFET / 学校教育 / MOS集積回路 / CMOSプロセス |
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| Research Abstract |
It is significant for an education of semiconductor engineering that CMOS integrated circuits can be fabricated because of their utility. A purpose of this study is to find a CMOS process for the education that impurity doping is made only with thermal diffusion method. The process that does not need expensive facilities such as ion implantation facility is convenient in national college of technology. Concretely, fabrication of an inverter-circuit, that is the simplest CMOS device was an aim of the study.
In the first half of a study, a condition to form deep diffused layer called p-type well on the n-type Si wafer was examined and a formations of PN junction between the well and the wafer were confirmed. Also, the formation of PN junction between the p-type well and n-type diffused layer on it was confirmed.
In the latter half of the study, a trial fabrication of the inverter circuit was made. The gate-length of the MOSFETs was designed by 50μm. In the fabrication process, eight pieces of hand-made photo-mask were used. Only one of ten pieces of samples operated as the inverter not enough. However, the fabrication possibility of CMOS device was confirmed fully.
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