| Project/Area Number |
13680415
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Kwansei Gakuin University (2002)
Osaka University (2001) |
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Principal Investigator |
ISHIURA Nagisa Kwansei Gakuin University School of Science and Technology, 理工学部, 教授 (60193265)
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| Co-Investigator(Kenkyū-buntansha) |
YAMAUCHI Hitomi Okayama Prefectural University, Department of Communication Engineering, 情報工学部, 助手 (10275373)
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| Project Period (FY) |
2001 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2002: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2001: ¥2,200,000 (Direct Cost: ¥2,200,000)
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| Keywords | retargetable compiler / DSP / digital signal processing / embedded processor / codesign / ターゲッタブルコンパイラ / 組込みプロセッサ |
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| Research Abstract |
In this project, we conducted a research on codesign methodology for software and hardware of application specific DSPs focusing on the problem of birdging "a gap between datapath configurations and instruction sets". Specifically, we have developed a retargetable compiler, a code compressor, and a control part generator, which target user-defined datapaths with irregular configurations. The retargetable compiler takes C programs and generates horizontal codes for the datapath. The code compressor reduces the code length by a dictionary based method, which is in a sense a replacement of instruction set design. The control part generator synthesizes a controller for the datapath to make it a complete DSP. We also conducted a case study of our "datapath oriented" codesign methodology on a G.723 voice compressor.
As for the retargetable compiler, we have developed methods for instruction selection, binding, and scheduling so that code would be generated within a feasible amount of time even for large basic blocks consisting of more than 100 operations. Especially, we have developpeda spill code insertion mechanism that never fails even for irregular datapaths and a register lifetime sequentialization algorithm to minimize the spill code insertion count. In a experiment where codes were generated for a dedicated datapath for G.723 and their two variations, we found that we can examine trade-offs between hardware cost and execution cycles.
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