| Project/Area Number |
13835002
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Institution | The University of Tokyo |
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Principal Investigator |
HIROSE Akira Graduate School of Frontier Sciences, Associate Professor, 大学院・新領域創成科学研究科, 助教授 (70199115)
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| Project Period (FY) |
2001 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥4,200,000 (Direct Cost: ¥4,200,000)
Fiscal Year 2002: ¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 2001: ¥2,900,000 (Direct Cost: ¥2,900,000)
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| Keywords | recurrent neural network / delay-tune equality / signal-voltage symmetry / analog circuit / associative memory / recall characteristics / ニューロ・チップ / コヒーレント型ニューラツネットワーク / P-SOM / 自己組織化 / 無線通信 / 高周波信号処理 / 適応復調 / 雑音 |
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| Research Abstract |
Neural networks have to be implemented as an analog hardware (non-pulse type) when used for high-frequency applications (ultra high speed signal processing) or as a massively parellel interface (ultra highly parallel processing). Nevertheless, the analog neural networks have not been investigated widely because oft the unstable behavior affected by noise (including insufficient accuracy of weights and large drift). The characteristics and origins of timing instability, distortion and noise spectrum in high frequency regions has still been unclear. We aim at realizing an effectively useful analog hardware by elucidating the origin of such weakness. We conducted measurement of characteristics of two kinds of associative memories (recurrent networks) ; i. e., a discrete component network and a VDEC custom chip network. The measurement results showed that the recalling process is affected to a great extent by the symmetry of the neuron-unit circuit and the synaptic resistors. Therefore, we have designed two new circuit elements (1)highty signal-voltage-symmetric synaptic resistors and (2)highly delay-time-equal neuron. We have fabricated a new network chip incorporating them through the VDEC and measured the characteristics. We have demonstrated that our chip has an outstanding recalling performance and the symmetry and the delay-tune equality has a critical influence on such recurrent decision circuit. The new circuit elements are applicable to recurrent decision chips in general including future ultra-fast turbo decoders.
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