| Project/Area Number |
14350177
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
電子デバイス・機器工学
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| Research Institution | Saitama University |
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Principal Investigator |
MYOREN Hiroaki Saitama University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (20219827)
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| Co-Investigator(Kenkyū-buntansha) |
TAKADA Susumu Saitama University, Faculty of Engineering, Professor, 工学部, 教授 (80282424)
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| Project Period (FY) |
2002 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥8,800,000 (Direct Cost: ¥8,800,000)
Fiscal Year 2004: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2003: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2002: ¥5,800,000 (Direct Cost: ¥5,800,000)
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| Keywords | Double Relaxation Oscillation SQUID / Flux Locked-Loop / Superconducting Latching Logic / Single Flux Quantum Logic Circuits / Up / Down Counter / D / A Converter / 2-Phase Power Supply / Cell Library / 単一磁束量子論理回路 |
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| Research Abstract |
On-chip double relaxation oscillation SQUID(DROS) with a superconducting digital flux locked-loop(FLL) circuit is demonstrated far high sensitive magnetic flux sensor and SQUID amplifier. In this study, we examined two kinds of superconducting digital FLL circuits : one was composed of a 8-bit up/down counter and a 8-bit R-2R ladder-type D/A converter designed using 4JL-gates which are driven by a two phase power supply at a frequency up to 4GHz. The other one was composed of an on-chip FLL circuit based on a Josephson counter and a 6-bit up/down counter using SFQ logic gates.
In the up/down counter, we used binary carry lookahead(BCL) circuits for high-speed operation. Logic simulations for the 4JL 8-bit up/down counter with BCL circuits showed correct up-and down-counting operation at 4GHz clock frequency assuming a 2.5kA/cm^2 Nb/Al-AlO_x/Nb junction technology. We expected that a DROS with the superconducting digital FLL circuit has large slew rate as high as 10-7Φ_0/s.
Using the 6-bit up/down counter using SFQ logic gates, logic simulations showed the correct up and down counting operation up to 33GHz and we expected that a DROS with the SFQ digital FLL circuits can be operated at 10GHz.
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